Content originally posted in LPCWare by Ian Lewis on Thu Jan 08 08:36:50 MST 2015
Hello,
I'm currently designing a board with an LPC4337 on. I will have a 19.2MHz VCTCXO on the board, and would like to use that to clock the LPC4337.
The VCTCXO has a clipped-sine output (not square wave) of ~800mV peak-to-peak. This complies with the datasheet requirements of <1.2V on the XTAL pins, and >200mV rms for the XTAL input.
The datasheet also says that the input should be high for between 40% and 60% of the time, and low for between 40% and 60% of the time. However, I can't find anything that says what levels it considers to be high and low! Neither can I find anything about permissible rise and fall times. I'm concerned that a clipped sine wave may spend too much time in an in-between region and the device won't work.
Can anybody shed any light on this? What levels are considered high and low? What rise/fall times are permissible? Has anyone used a clipped sine wave to drive the external input?
I suppose the alternative is to square the signal up with a buffer, and resistively divide down to below 1.2V, but I'd rather avoid the extra components if they're not needed.
One more question: Figure 42 in the datasheet (Slave mode operation of the on-chip oscillator) shows the clock capacitively coupled to the input via 100pF (this is fine) and also an additional capacitor to ground, labelled Cg. I can't find what value Cg is supposed to be, or even whether its supposed to represent a physical capacitor, or the stray capacitance of pads/tracks. Can anyone enlighten me on this?
Many thanks,
Ian.
