@Badman We have tried with your solution and its working.
The Main clock frequency is 96 Mhz and setting SYSTICKCLKDIV0 register with zero (divide by 1). With Systick handler giving interrupt at every 100ms (calculated based on freq=96 Mhz), the code is not interrupted at the handler.
But with setting SYSTICKCLKDIV0 register with 1 (divide by 2), we get 48 Mhz. With above 48 Mhz, and given Systick interrupt value at 100 ms (calculated based on freq = 48 Mhz), the handler is getting hit. So, we are assuming the main clock is 48 Mhz instead of 96 Mhz.
So, Can you help me in getting the reasoning why the code is not working with 96 Mhz?
Our modification in clock registers:
SYSCON->SYSTICKCLKDIV0 = 0x00; // systick clk divide with one
SYSCON->SYSTICKCLKSEL0 = 0x00; //selecting main clk for systick from syscon (96 MHZ)
SYSTICK->SYST_CSR |= (1 << 1); // enable interrupt to systick (100msec)
SYSTICK->SYST_CSR &= ~ (1 << 2); // enable external clk
SYSTICK->SYST_CSR |= (1 << 0); // systick counter enable