EMC Address to Address Line Translation External SDRAM

[praveenth_sanmu]

Hello guys,

I am currently using the LPC4370 with 4 external SDRAMs. I am using the following configuration 32Mx16 4BANKS 13ROWS 10COLS (32bit external bus high performance address assignment row, bank, column). Two 16-bit SDRAMs are connected to a dynamic chip selection, so I have twice a 32-bit external memory architecture. I can read and write all external SDRAMs with the addresses: 0x28000000 - 0x37FFFFFF

I'd like to know the translation of the address range into row and column and bank.

I did some measuremnets:

I wrote data to the addresses 0x28000000, 0x28000004, 0x28000008, 0x2800000C and few other addresses to have independent write access. (See figures below)

I write always a 32-bit number on the external SDRAM.

No address lines were used for the above mentioned addresses (0x28000000-0x2800000C) (== no signal was seen on the oscilloscope).

When writing to address 0x2800000010, address line A2 was active (expected behavior).

How is it possible that the address lines A0 and A1 are never activated when writing addresses 0x28000000, 0x28000004, 0x28000008, 0x2800000C (I also checked other 14 address lines, none of them seem to be activated)?

My expectation is that for writing to 0x28000004 the address line A0 should be enabled, writing data to 0x28000008 A1 should be enabled and writing data to 0x2800000C A0 and A1 should be enabled.

[xiangjun_rong]

Hi, Praveenth,

Regarding your question that if the low address are driven when you access SDRAM, I think it is dependent on the accessing mode for example if you use Burst mode or random mode. If you use burst mode,and the burst length is 8, and you access in 32 bits mode, the column address will be constant in the burst process. In the random mode, the column address will change with the accessing process. It is difficult to observe the A0/A1/A2... address, because you have to know the COMMAND of the accessing process for example activate command, read command..., because the address are reused in the process.

Hope it can help you

BR

Xiangjun Rong

[praveenth_sanmu]

The configuration I use is as follows:

/* Base Address */     

  EMC_ADDRESS_DYCS0, 

/* RAS value (Number of EMC_CCLK cycles) */

  3,

/* Mode Register value */

EMC_DYN_MODE_WBMODE_PROGRAMMED |
EMC_DYN_MODE_OPMODE_STANDARD |
EMC_DYN_MODE_CAS_3 |
EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
EMC_DYN_MODE_BURST_LEN_4,

/* Dynamic Configuration value */

EMC_DYN_CONFIG_DATA_BUS_32 |
EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS |
EMC_DYN_CONFIG_MD_SDRAM 

The same applies to the DYCS1.

Then it would make sense that I don't see the address line A0 and A1, because I use the burst mode with 4 bytes.

But I also tried to change the burst mode to 1 byte bursts or even bits, but A0 and A1 didn't appear at low addresses only at high addresses

I have also made some other observations which I cannot guess why it is so.

Activated Address Line     Address where data is written

A2                                      16

A3                                      32

A4                                      64

A5                                      128

A6                                      256

A7                                      512

A8                                      1024

A9                                      2048

A10                                    Precharge Signal (Continuos alternating)

A11                                    4096

A12                                    671088

A13                                    4096

A14                                    8192

A0                                      16384

A1                                      32768

If you have a look at the table, you see the the address lines are activated for the first time at power of two addresses.

A13 and A14 are bank address lines.

A0 and A1 seem to be used as address lines "A15 and A16", which makes sense for the selected burst mode.

The behaviour of address lines A11 - A14 seem to be different. Somehow it does not fit into my assumptions.

My assumptions:

- Row, Bank, Column address mapping

  --> First all rows assinged, when all the address lines for the row addresses are used (2^13 addresses) then the bank address line would be used and then when all bank addresses and row addresses are used (2^13 * 2^4) then column addresses will be used

Based on this information, can you help me find the schema of how to translate an address into the address lines (A0-A14)?