CPU Delay After Changing M4MEMMAP - LPC4337

[MikeBrennan]

LPC4337

Have someone who is developing a boot loader which changes the CREG M4MEMMAP register to “shadow” an embedded application stored flash but is linked to 0x0.  He has this working but am noticing that the change in the memory map does not take effect immediately, in fact,  t seems he needs to insert at least 4 instructions before the next read from the “shadowed” memory region to make it work.

The documentation does not seem to mention such a delay.

Can you provide detail as to the exact delay (or suggested instruction sequence) following a change to this register?

[MikeBrennan]

Any feedback on this?

Thanks,
Mike

[Carlos_Mendoza]

Hi Michael,

What you mention may be a data synchronization issue. You can try using the isb and dsb intructions to flush the pipeline and ensure that all previous instructions are completed before executing new instructions, these are instructions of the ARM core which help to synchronize code execution and data accesses to avoid undesired behaviors.

You can find more information on this link:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHEDAAF.html

Hope it helps!

Best Regards,
Carlos Mendoza
Technical Support Engineer