Dear NXP,
We are designing a bootloader for customer product firmware update. In LPC54114 mutlicore application, there are M4 and M0 core and they have their own output bin file (axf). The question is how to implement the bootloader design and which memory address the output files (M4 & M0) should flash in?
Thanks,
Eric
HI Eric
I suggest you refer AN12123
https://www.nxp.com/docs/en/application-note/AN12123.pdf
memory allocation is defined in "MCU settings" of each slave and master project, for example
please note, you need build slave project first then build master project. master will link slave code. when download master code to flash, slave code will be download to flash as well.
Have a nice day,
Jun Zhang
Hi NXP,
I think I am having a similar question as Eric while I have already had a working SBL for m4 only application firmware.
Now my problem is how should I IAP an application firmware that use both m4 and m0+ and how to invoke it from SBL?
Best Regards,
Ken
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What I have done and achieved:
Testing 1 - it works with GPIO:
Testing 2 - it works after adding PININT:
Testing 3 - FAILED