ADC Frequency and Sample rate in LPC55xx

[pejo]

Hi!

I'm configuring ADC Conversion in my LPC5504. 

Currently the configuration is the following:

* Main Clock: 96MHz

* ADCK Configuration:

  - CLOCK_SetClkDiv to Prescaler = 2   (48MHz)

* 10 conversion operations:

  - 9 with 35 ADCK cycles total sample time

  - 1 with  131 ADCK cycles total sample time

* Conversion start trigger:

  - Callback function in PWM at 10KHz

This is already working.

In the document from the NXP Knowledge base "ADC multi-channel sampling and DMA transfer in LPC55xx" it is said that maximum frequency is 24MHz but as I said we selected ADCK to 48MHz.

Question #1 Should we set a smaller prescaler (4 instead) according to this limitation or we could even use prescaler=1 ?

In this same document and in the user manual it is said that maximum sample conversion is 1 Mega samples per second. In our case we are doing 10 conversions at 10kHz which are 100,000 conversions pers second

Question #2 should I understand that we are still under the limitation of 1MSPS ?

[Alice_Yang · Accepted solution]

Hello @pejo 

For details about the ADC clock frequency and sample rate, please refer to the Datasheet.

Thank you.

BR

Alice