A board implemented with LPC1850 has DEBUG and clock problems

[lpcware]

Content originally posted in LPCWare by MKai on Tue May 27 06:17:34 MST 2014
  I have implemented a board with LPC1850, Now, I have soldered the following components ob the board:
    (1) 30 filter capacitor of 0.1uF.
    (2) The pull-up resistor of DEBUG Enable pin.
    (3) The switch of #ISP pin.
    (4) The switch of P2_9, P2_8, P1_2, P1_1.
    (5) The interface of JTAG.
    (6) A 32.768KHz oscillator to RTCX1 and RTCX2 matching capacitor.
    (7) A 12MHz oscillator to XTAL1 and XTAL2 matching capacitor.
  I have a main board with power module and other devices, and I could make sure the power module work well.
  Now, I just want to use the on-chip RAM to do some debug. So I haven't soldered other chips.
  Case 1: When I pull the #ISP pin high and pull the pins of P2_9, P2_8, P1_2, P1_1 high, and the board power up, I test the CLK1 pin using  oscilloscope, getting wave of 16~20MHz with some noice. In this case, I connect the board to a PC through ULINK2, and when I open debug in Keil, it will info me "SWD Communication Failed".
  Case 2: Then, I pull the #ISP pin low and keep others. I test the CLK1 pin, getting wave of 67~68MHz. When I open debug in Keil, it could connect successfully. But many registers could not be read("Connot access memory") and written.
  I'm not sure that the two oscillators start successfully, and I wonder if it has some influence to debug when start fails. After reading the user manual, I think the CLK1 pin should has 12MHz output in Case 1 and 96MHz in Case 2. What could cause the abnormal clock output? Could someone analyse my case and give me some help?
  Many thanks!

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Jun 30 04:43:17 MST 2014
Here are a few remarks to your board design.

[list]
  [*]  The chip always starts with the internal 12MHz RC oscillator, the bootloader does not switch on the external oscillator, except for the USB bootmode (because of higher accuracy)
  [*]  The SWDIO signal requires a pull-up resistor
  [*]  The condition with P2_9, P2_8, P1_2, P1_1 on high is in principle an undefined boot mode, I would go for all on low as default
  [*]  The pin CLK1 is not a clock output after reset, so I don't expect to see any clock on it. None of the boot modes configures the SDRAM interface, so to see a meaningful clock on this pin you need to configure it with a debugger script. After reset there is no pin configured to provide a clock output. "If" the bootloader configures such a pin (which I don't believe), or if you configure such a pin with a debugger script, then you should see a stable frequency with 3.3V swing.
  [*]  When you enable ISP mode with #ISP pin on low, then the system hangs up in a loop waiting for the character '?' on UART0. This is a relatively good start condition for getting access with a debugger, because no application code is executed, the system just stays in the bootloader.
  [*]  Messages like "Cannot access memory" can happen for the following reasons: the memory locations do not exist - or the memory locations do not exist yet. Imagine that you have the debugger memory window open, asking for memory at 0x28000000. This is an SDRAM memory area and there will be problems to read if the SDRAM interface is not set up yet. Solution is to close this windows so that at debuuger start this memory area is not checked.
  [*]  Debugger scripts could try to write registers which cannot be accessed, this would also generate this message.
  [*]  Think about the frequencies which you want to attenuate in your board design. In nowadays designs we have sometimes higher frequencies which don't get attenuated by the 100nF capacitors at all, 10nF or 1nF would maybe make more sense.
  [*]  Please check if you a 100nF capacitor on the reset pin. If yes, then please remove it or make it a 1nF (depending on the value of the pull-up resistor). The time constant should be short.
[/list]


Regards,
NXP Support Team