4370 slower than 1769

[lpcware]

Content originally posted in LPCWare by JoeE on Sat May 31 04:29:13 MST 2014
Hello,
in my application (polyphonic synthesizer) I configured a timer to generate an interrupt every 20 µsec (50 kHz). The interupt service routine calls a subroutine doing plenty of calculations and transferring a value via SSP1(at 4 MHz) to an external 12 bit DAC. As I needed more speed I switched from an LPCxpresso 1769  board running at 120 MHz to an LPC-Link 2 board running a lpc4370 at 204 MHz. However the 4370-board is significantly slower. The interrupt service routine takes 9 µsec on the 1769 whereas it takes 22 µsec on the 4370. I determined this by toggling a GPIO-pin at the begin and the end of the interrupt service routine and measuring the pulse length with a scope (and a period counter). Does anybody have an explanation for this behaviour. I am using the LPCXpresso IDE and in case of the 4370 board LPCOpen. The code for the Interrupt service routine ist the same. The code optimization level is also the same in both cases.
JoeE

[lpcware]

Content originally posted in LPCWare by mc on Sat May 31 06:03:18 MST 2014
Hi JoeE,
II would like to extend what Mike has said. It also depends on the speed of the external QSPI flash. What is the SPIFI clock and execution speed ? This board contains W25Q80 QSPI flash which can run upto 80MHz. so you effective speed in quad mode will be less than or equal to 40MHz, however you can run SPIFI interface at 102MHz and Core at 204MHz.

[NVazquez]

I am trying to configure W25Q80DV with LPC54016.

This is the configuration I am using,

#ifdef W25Q80DVSIG
/* SPIFI Descriptor - W25Q80DVSIG */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr
(void (*)(void))0x001440EF, // mfgId + extCount for W25Q80DV
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x1301001D, // caps
(void (*)(void))0x0000000F, // Blks + RESV1 for W25Q80DV
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
(void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endif

I want to read and write the memory. The clk is 12mhz. Not sure if it is the configuration or something else. Any help is appreciated. 

Thank you!

[NVazquez]

I am trying to configure W25Q80DV with LPC54016.

This is the configuration I am using,

#ifdef W25Q80DVSIG
/* SPIFI Descriptor - W25Q80DVSIG */
(void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr
(void (*)(void))0x001440EF, // mfgId + extCount for W25Q80DV
(void (*)(void))0x00000000, // extid 0-3
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x1301001D, // caps
(void (*)(void))0x0000000F, // Blks + RESV1 for W25Q80DV
(void (*)(void))0x00010000, // blkSize
(void (*)(void))0x00000000, // reserved
(void (*)(void))0x00000100, // pageSize + RESV2
(void (*)(void))0x00003F00, // maxReadSize
(void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
(void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
(void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
#endif

I want to read and write the memory. The clk is 12mhz. Not sure if it is the configuration or something else. Any help is appreciated. 

Thank you!

[lpcware]

Content originally posted in LPCWare by mch0 on Sat May 31 05:05:53 MST 2014
From where do you execute the code?
If from SPIFI then the execution speed of the CPU is severely bandwith limited. I'd assume without measurement you end up at an effective rate of something like 20-30 MHz ...effective instruction issue frequency at most.
The LPC1969 usually executes from internal flash, which in this case is much faster.

To see the 204 MHz really in action (CPU-wise) you best execute from one of the local SRAMs.

Mike