180MHz CLOCK CONFIGURATION DONE BUT WAVEFORM IS NOT SHOWING ON CLOKOUT PIN PIO0_16

[k_sunilgupta]

I have config the cpu clock 180mhz via clock configuration tool but when i want to see the waveform of 180mhz is not showing on CRO. I am using PIO0_16 CLOCKOUT pin to show the waveform.

here is the code,

void BOARD_BootClockRUN(void)
{
/*!< Set up the clock sources */
/*!< Set up FRO */
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
being below the voltage for current speed */
/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
before calling this API since this API is implemented in ROM code */
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
POWER_SetVoltageForFreq(180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */

/*!< Set up SYS PLL */
const pll_setup_t pllSetup = {
.pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U) | SYSCON_SYSPLLCTRL_DIRECTO_MASK,
.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
.pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(2U)),
.pllRate = 360000000U,
.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
};
CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */

/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U, false); /*!< Reset divider counter and set divider to value 2 */
CLOCK_SetClkDiv(kCLOCK_DivClkOut, 0U, true); /*!< Reset CLKOUTDIV divider counter and halt it */
CLOCK_SetClkDiv(kCLOCK_DivClkOut, 2U, false); /*!< Set CLKOUTDIV divider to value 2 */

/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
CLOCK_AttachClk(kSYS_PLL_to_CLKOUT); /*!< Switch CLKOUT to SYS_PLL */
SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
/*!< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

[k_sunilgupta]

still not found the answer for register level programing

 SYSCON->PDRUNCFGCLR[0] &=~ (1UL << 4); // FRO_ON
SYSCON->MAINCLKSELA = 0x0U;       // FRO 12MHz
    
SYSCON->SYSPLLCTRL |= (32U << 4);      // SEI
SYSCON->SYSPLLCTRL |= (16U << 15);    // SELP
SYSCON->SYSPLLCTRL |= (0U << 10);      // SELR
SYSCON->SYSPLLMDEC = 8191U;            // M VALUE
SYSCON->SYSPLLNDEC = 770U;              // N VALUE
SYSCON->SYSPLLPDEC = 66U;                // P VALUE
SYSCON->SYSPLLCLKSEL = 0x0U;           // FRO 12MHz
SYSCON->CLKOUTSELA = 0x4U;              // PLL SELECT
SYSCON->CLKOUTDIV = 1U;                    // CLOCK OUT DIVISON

above code is not working... please suggest

[xiangjun_rong]

Hi

I suggest you refer to the clock configuration of LPC54628, like this:

BR

XiangJun Rong

void BOARD_BootClockPLL220M(void)
{
/*!< Set up the clock sources */
/*!< Set up FRO */
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
being below the voltage for current speed */
POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */

/*!< Set up SYS PLL */
const pll_setup_t pllSetup = {
.pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U),
.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)),
.pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)),
.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
.pllRate = 220000000U,
.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
};
CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
before calling this API since this API is implemented in ROM code */
CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */

/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Set USB0CLKDIV divider to value 2 */

/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /*!< Switch USB0_CLK to FRO_HF */
SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK;
}

pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
{
uint32_t inRate;
pll_error_t pllError;

/* Determine input rate for the PLL */
if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
{
inRate = pControl->inputRate;
}
else
{
inRate = CLOCK_GetAudioPLLInClockRate();
}

/* PLL flag options */
pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
pSetup->pllRate = pControl->desiredRate;
return pllError;
}

/* Setup PLL Frequency from pre-calculated value */
/**
* brief Set PLL output from PLL setup structure (precise frequency)
* param pSetup : Pointer to populated PLL setup structure
* return kStatus_PLL_Success on success, or PLL setup error code
* note This function will power off the PLL, setup the PLL with the
* new setup data, and then optionally powerup the PLL, wait for PLL lock,
* and adjust system voltages to the new PLL rate. The function will not
* alter any source clocks (ie, main systen clock) that may use the PLL,
* so these should be setup prior to and after exiting the function.
*/
pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
{
if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
{
/* Turn on the ext clock if system pll input select clk_in */
CLOCK_Enable_SysOsc(true);
}
/* Enable power VD3 for PLLs */
POWER_SetPLL();
/* Power off PLL during setup changes */
POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);

/* Write PLL setup data */
SYSCON->SYSPLLCTRL = pSetup->pllctrl;
SYSCON->SYSPLLNDEC = pSetup->pllndec;
SYSCON->SYSPLLNDEC = pSetup->pllndec | (1UL << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
SYSCON->SYSPLLPDEC = pSetup->pllpdec;
SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
SYSCON->SYSPLLMDEC = pSetup->pllmdec;
SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */

/* Flags for lock or power on */
if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0UL)
{
/* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);

/* Initialize and power up PLL */
SYSCON->SYSPLLMDEC = maxCCO;
POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);

/* Set mreq to activate */
SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);

/* Delay for 72 uSec @ 12Mhz */
SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);

/* clear mreq to prepare for restoring mreq */
SYSCON->SYSPLLMDEC = curSSCTRL;

/* set original value back and activate */
SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);

/* Enable peripheral states by setting low */
POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
}
if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
{
while (CLOCK_IsSystemPLLLocked() == false)
{
}
}

/* Update current programmed PLL rate var */
s_Pll_Freq = pSetup->pllRate;

return kStatus_PLL_Success;
}

[k_sunilgupta]

its LPC54606J512BD100

[k_sunilgupta]

its LPC54606J512BD100

[k_sunilgupta]

If you could help me to config clock 180mhz via register level then it would be very helpful for me.

[k_sunilgupta]

and also want to write same code on register level but not work 

this is the code for register level but its not working

 SYSCON->PDRUNCFGCLR[0] &=~ (1UL << 4); // FRO_ON
SYSCON->MAINCLKSELA = 0x0U;       // FRO 12MHz
    
SYSCON->SYSPLLCTRL |= (32U << 4);      // SEI
SYSCON->SYSPLLCTRL |= (16U << 15);    // SELP
SYSCON->SYSPLLCTRL |= (0U << 10);      // SELR
SYSCON->SYSPLLMDEC = 8191U;            // M VALUE
SYSCON->SYSPLLNDEC = 770U;              // N VALUE
SYSCON->SYSPLLPDEC = 66U;                // P VALUE
SYSCON->SYSPLLCLKSEL = 0x0U;           // FRO 12MHz
SYSCON->CLKOUTSELA = 0x4U;              // PLL SELECT
SYSCON->CLKOUTDIV = 1U;                    // CLOCK OUT DIVISON

[k_sunilgupta]

LPC54606J512BD100 

this one i am using,

[xiangjun_rong]

Hi,

Pls try to use the following code:

void outputCLKO(void)
{
CLOCK_EnableClock(kCLOCK_Iocon);
//select main_clk clock as CLKOUT outputting clock
SYSCON->CLKOUTSELA=0x00;
const uint32_t port0_pin16_config = \
(/* Pin is configured as CLKOUT*/
IOCON_PIO_FUNC2 |
/* No addition pin function */
IOCON_PIO_MODE_INACT |
/* Standard mode, output slew rate control is enabled */
IOCON_PIO_SLEW_STANDARD |
/* Input function is not inverted */
IOCON_PIO_INV_DI |
/* Enables digital function */
IOCON_PIO_DIGITAL_EN |
/* Open drain is disabled */
IOCON_PIO_OPENDRAIN_DI);
/* PORT3 PIN12is configured CLKOUT */
IOCON_PinMuxSet(IOCON, 0U, 16U, port0_pin16_config);
/*divider is 256*/
SYSCON->CLKOUTDIV=0xFF;
while( SYSCON->CLKOUTDIV&0x80000000) {}
__asm("nop");
//SYSCON->CLKOUTSELA=0x00;
}

Hope it can help you

BR

XiangJun Rong

[xiangjun_rong]

Hi,

Can you tell us the part number you are using?

BR

XiangJun Rong