CAN frames do not guarantee an edge appears for every bit. There can be sequence of up to five consecutive bits of the same logic level with no edges appearing in the waveform.
If the bus is operating normally and frames are being transferred without error then towards the end of the frame the acknowledge slot will be dominant (CAN_H is high and CAN_L is low). The bit immediately preceding (CRC delimiter) and following (acknowledge delimiter) will be recessive (CAN_H and CAN_L are almost the same voltage). Therefore it is always possible to measure the width of the acknowledge slot and determine the bit rate.
"FAQ contribution from Embedded Systems Academy, experts in CAN bus. For more information visit www.esacademy.com"
