Hi, Serdar,
For you application to sample two channels at a fixed cycle time, read two sample by DMA, enter ISR after sampling 4000 samples, I think you can use the following solution.
As you know that the K64F has one PDB module and two 16 bits ADC modules, and DMA module, you can set up the PDB so that it can trigger two ADC module at a fixed cycle time, after the ADC conversion is over, the ADC can trigger DMA module so that the DMA can transfer the two samples to memory without core involvement, after the DMA transfer 4000 samples, the DMA can generate interrupt.
For the PDB module, it has 4 channels, the channel0 triggers ADC0, the channel1 triggers ADC1, you can set up the PDB0_MOD to determine the sampling cycle time, set the PDB0_CH0DLY0 to define the ADC0 sampling instant, set the PDB0_CH1DLY0 to define the ADC1 sampling instant. The PDB is set up in software triggering mode instead of external triggering mode.
For the ADC0/ADC1, both of them are set up in hardware triggering mode.
for the DMA, I suppose you can use ONE DMA channel to read both ADC0/ADC1 result registers to memory in the minor loop, you set up the major loop counter as 2000, after 4000 samples has been transferred, the DMA will enter it's own interrupt.
Hope it can help you.
BR
Xiangjun Rong