Reasons for large ADC quantization error (TWR-K60D100M) ?

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Reasons for large ADC quantization error (TWR-K60D100M) ?

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jerrylian
Contributor IV

I am copying codes from KSDK demo with the following ADC setting and configurations:

* ADC input: ramp-up wave at 1Hz, 0 - 3 volt

* Calibration: roughly 0v == -32768; 3v == +32768

* Sampling frequency: 1 KHz

* As can be seen, there are only 33 quantization steps, instead of 65536 (2^16) steps .

              (or should at least have 1000 steps, as the sampling frequency is 1 KHz, right?)

Anything wrong with my ADC configurations?

Thanks,

Jerry

===== ADC configuration: 16 bit, single-end, long sample time disabled, high speed enabled, ... ============

{
adc16_config_t adc16ConfigStruct;
adc16_channel_config_t adc16ChannelConfigStruct;

/*
* adc16ConfigStruct.referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
* adc16ConfigStruct.clockSource = kADC16_ClockSourceAsynchronousClock;
* adc16ConfigStruct.enableAsynchronousClock = true;
* adc16ConfigStruct.clockDivider = kADC16_ClockDivider8;
* adc16ConfigStruct.resolution = kADC16_ResolutionSE12Bit;
* adc16ConfigStruct.longSampleMode = kADC16_LongSampleDisabled;
* adc16ConfigStruct.enableHighSpeed = false;
* adc16ConfigStruct.enableLowPower = false;
* adc16ConfigStruct.enableContinuousConversion = false;
*/
ADC16_GetDefaultConfig(&adc16ConfigStruct);
adc16ConfigStruct.clockDivider = kADC16_ClockDivider1;
adc16ConfigStruct.enableHighSpeed = true;
adc16ConfigStruct.resolution = kADC16_ResolutionSE16Bit;
ADC16_Init(DEMO_ADC_BASE, &adc16ConfigStruct);
#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
       ADC16_EnableHardwareTrigger(DEMO_ADC_BASE, false);
       if (kStatus_Success == ADC16_DoAutoCalibration(DEMO_ADC_BASE))
              PRINTF("ADC16_DoAutoCalibration() Done.\r\n");
      else PRINTF("ADC16_DoAutoCalibration() Failed.\r\n");

#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */

ADC16_EnableDMA(DEMO_ADC_BASE, true);

adc16ChannelConfigStruct.channelNumber = DEMO_ADC_USER_CHANNEL;
adc16ChannelConfigStruct.enableInterruptOnConversionCompleted = false; /* Enable the interrupt. */
#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
     adc16ChannelConfigStruct.enableDifferentialConversion = false;
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
ADC16_SetChannelConfig(DEMO_ADC_BASE, DEMO_ADC_CHANNEL_GROUP, &adc16ChannelConfigStruct);
}

======================================================================================

k60-adc-1Hz.png

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jerrylian
Contributor IV

Thanks Xiangjun, Mark:

I solved the problem, it is my fault:

* I created a circular buffer of 30 taps, but I always plotted the first tap by mistake. (so 33 steps * 30 taps ~= 1 KHz )

* Attached you will see the correct result.

k60-adc-1Hz-good.png

Thanks again for all your response!

Jerry

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jerrylian
Contributor IV

Thanks Xiangjun, Mark:

I solved the problem, it is my fault:

* I created a circular buffer of 30 taps, but I always plotted the first tap by mistake. (so 33 steps * 30 taps ~= 1 KHz )

* Attached you will see the correct result.

k60-adc-1Hz-good.png

Thanks again for all your response!

Jerry

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Jerry,

First of all, assume the analog waveform is 1HZ, the ADC sampling frequency 1KHz, you should get the 1000 steps instead of 32 steps, because 1KHz/1hz=1000. Pls check if you use hardware triggering mode, secondly, pls check the triggering source.

If yuou use single ended analog mode and 16 bits ADC resolution, if the analog voltage is 0V, the digital sample is 0, if the analog voltage is 1.67V, the digital sample is 0x7FFF, if the analog voltage is 3.3V, the digital sample is 0xFFFF. So i think the Figure coordinator is incorrect, you should draw with Y cooridimator from 0 to 0xFFFF rather than from -33000 to +33000, there is NOT negative voltage, in other words, the sample variable should be unsigned short type instead of signed short type.

Pls have a try to change the Y coordinator and check the ADC triggering source signal frequency.

BR

xiangjun Rong

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mjbcswitzerland
Specialist V

Hi

It is not visible how the sampling frequency is controlled and possibly that is the actual problem.

Slow the ramp and see what happens - if the step size reduces but the steps take place at the same rate you are sampling much slower than 1kHz, which would result in big steps. If the step size stays the same but the steps take place slower it is indeed a quantization effect.

Regards

Mark

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jerrylian
Contributor IV

Hi, Mark:

Thanks for your hints. ADC is soft-triggered (but not shown above), and I am pretty sure it is 1 KHz.

Could "long-sample-time-disabled" or "high-speed-enabled" be the causes?

Jerry

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mjbcswitzerland
Specialist V

Jerry


The worst possible resolution is 8 bit and the slowest possible conversion time is about 170us so I don't think that even using strange settings would give such low resolution at the ADC so the only possibility I see is either measurement/SW error outside of the ADC part.

I have used the same chip in industrial designs (using the uTasker project) and we always had accuracy/resolution as expected (16 bit accuracy will never be achieved since the max physical accuracy is equivalent to about 12.5 bits with max. averaging).

One reference configuration in the uTasker project is to do HW transfers from an ADC input to a DAC output using DMA (whereby the DAC output limits resolution to 12 bits) and it is simple to see that the output follows the input (also with no SW running) with the expected resolution. This is described in http://www.utasker.com/docs/uTasker/uTaskerADC.pdf and enabled with TEST_AD_DA and can also be used to test custom HW to be sure that it is not something specific to the design/board. It can be downloaded from GITHUB in open source form: http://www.utasker.com/kinetis.html and ensures complete operation without having to fiddle with the NXP drivers.

Regards

Mark

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