Try enabling the PFE bit in the PORTx_PCRn register:
PFE = Passive Filter Enable
Passive filter configuration is valid in all digital pin muxing modes.
0 Passive input filter is disabled on the corresponding pin.
1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer
to the device data sheet for filter characteristics.
Hello David and Thanks
I don’t know if using PE I can configure PORTxPCRn register.
In my application I’m using two PortA inputs PTA1 & PTA2
To solve yours suggestion and I tried to use Pins1:PinSetting option.
There was no improvement in SW bouncing reduction.
I’m attaching my configuration.
I think that my configuration is wrong, using debugger I have seen that “PFE” remains low.
I think that using assembly can solve the problem but I don’t know how to do this (I have hardware experience).
Do you have any recommendations.
Using low pass filter (RC) at input solves the problem but I prefer software solution.
Two suggestions....use an interrupt on the PTA1/2 GPIO pins and in the interrupt have a delay loop. After delay loop if the signal is still asserted, then assume debounced and proceed. If signal was de-asserted then take not action. Positive is simple to implement. Negative it wastes time during debounce.
Other suggestion for K64 is to use a PORT D pin that has a digital filter capability and you can use hardware to do your debouncing.
Chapter 10 tells you that only PORT D pins have digital filter capability.
Chapter 11 has the "Digital Filter" registers for PORTD (PORTD_[DFER&DFCR&DFWR] to configure.
The fsl_port_hal.h has the MACRO's to access this stuff. Ex: static inline void PORT_HAL_SetDigitalFilterWidth(PORT_Type * base, uint8_t width)