KSDK SPI Driver performance

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

KSDK SPI Driver performance

460 Views
HeMyFAE
NXP Employee
NXP Employee

Dear KSDK support,

 

K22FN512 SPI clock set up to be around 18Mhz KDS 3.0 and KSDK 1.2 There seems to be quite a large delay between each transferred byte in the SPI data package. Attached is the generated Processor Expert code from the KSDK1.2 and the screen capture to that shows there is 81uSec delay in between each bytes compares to capture from a PSOC device which shows only 11uSec.

 

Please advise on how to improve the performance of the SPI. BTW the customer has also tested with KSDK 1.3 and the result is the same.

 

Regards, hy

Original Attachment has been moved to: spi_capture.zip

Original Attachment has been moved to: Source.zip

Labels (1)
0 Kudos
1 Reply

261 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Mai,

From register setting perspective, if you want to control the interval between two SPI transfer, you have to set up the DT(delay scaler) and PDT(delay prescaler) in SPIx_CTARn register. Unfortunately, the SPI bean in PE does not has location to set the delay, but you can use SPI hal function to set up the delay.

You can use the function to set up it.

int main(void)

/*lint -restore Enable MISRA rule (6.3) checking. */

{

  /* Write your local variable definition here */

  /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/

  PE_low_level_init();

  /*** End of Processor Expert internal initialization.                    ***/

  /* Write your code here */

  /* For example: for(;;) { } */

      OSA_Init();

    EDMA_DRV_Init(&dmaController1_State, &dmaController1_InitConfig0);

    //Rong wrote///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

     DSPI_HAL_SetDelay(FSL_DSPICOM1,kDspiCtar1, 0,1,kDspiAfterTransfer);

//////////////////////////////////////////////////////////////////////////////////////

    DSPI_DRV_EdmaMasterInit(FSL_DSPICOM1, &dspiCom1_MasterState, &dspiCom1_MasterConfig0, &dspiCom1_dmaTcd);

    DSPI_DRV_EdmaMasterConfigureBus(FSL_DSPICOM1, &dspiCom1_BusConfig0, &dspiCom1_calculatedBaudRate);//startup as slow bus

    static uint8_t header[5];

}

I copy the protype of the function in fsl_dspi_hal.h:

@brief Manually configures the delay prescaler and scaler for a particular CTAR.

*

* This function configures the PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK),

* after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay

* after transfer pre-scalar (PDT)and scalar (DT).

*

* These delay names are available in type dspi_delay_type_t.

*

* The user passes which delay they want to configure along with the prescaler and scaler value.

* This  allows the user to directly set the prescaler/scaler values if they have

* pre-calculated them or if they simply wish to manually increment either value.

*

* @param base Module base pointer of type SPI_Type.

* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type

*                  dspi_ctar_selection_t.

* @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).

* @param scaler The scaler delay value (can be any integer between 0 to 15).

* @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t

*/

void DSPI_HAL_SetDelay(SPI_Type * base, dspi_ctar_selection_t whichCtar, uint32_t prescaler,

                       uint32_t scaler, dspi_delay_type_t whichDelay);

BR

XiangJun Rong

0 Kudos