KL26Z SPI0 FIFO

[nobodyKnows]

Hello,

it seem that the SPI0 of the KL26Z has no FIFO. I get an Hardfault error if I try to write the SPI0->C3 register. But according to Page 681 in Reference Manual there is a SPI0_C3 register.

Best regards

[xiangjun_rong · Accepted solution]

Hi,

Pls refer to section 3.9.2 SPI configuration, only SPI1 has 4-deep FIFO of 16 bits entries, the SPI0 module does not have FIFO.

hope it can help you.

BR

Xiangjun Rong

I copy it here:

3.9.2.1 SPI instantiation information
The number of SPI modules on this device is: two
The supported data length is: 16-bit
SPI1 includes a 4-deep FIFO of 16-bit entries.
SPI0 is clocked on the bus clock. That is, the SPI0 module clock is connected to the chiplevel
bus clock.
SPI1 is clocked from the system clock. That is, the SPI1 module clock is connected to the
chip-level system clock. SPI1 is therefore disabled in Partial Stop Mode.
The SPI supports DMA request and can operate in VLPS mode. When the SPI is
operating in VLPS mode, it will operate as a slave.
SPI can wake the MCU from VLPS mode upon reception of SPI data in slave mode.

[nobodyKnows]

Thank you for that information.

*shaking head*