I2C Master is working if I'm using blocking I2C master transfers without interrupt enabled , but as soon as I try non blocking transfer which uses interrupt, CPU generates HardFault exception, after 1st byte(i2c slave address) gets transmitted.
Here is crash dump:
0> [Hard fault handler - all numbers in hex]
0> R0 = 0x0
0> R1 = 0x40
0> R2 = 0xf0
0> R3 = 0x0
0> R12 =0x 2000ff70
0> LR [R14] = 0xfffffff9 subroutine call return address
0> PC [R15] = 0x0 program counter
0> PSR = 0x28
0> BFAR = 0xe000ed38
0> CFSR = 0x20000 <-------INVSTATE bit is set main cause of the HardFault
0> HFSR = 0x40000000 <----- FORCED bit is set
0> DFSR = 0x0
0> AFSR = 0x0
0> SCB_SHCSR = 0x0
One of the ARM documentation says about INVSTATE bit:
Invalid state Usage Fault:
0 = no invalid state
1 = the processor has attempted to execute an instruction that makes illegal use of the Execution Program Status Register (EPSR). When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR.
Potential reasons:
a) Loading a branch target address to PC with LSB=0.
b) Stacked PSR corrupted during exception or interrupt handling.
c) Vector table contains a vector address with LSB=0.
I'm wondering if anybody encountered such a problem when using I2C Master driver from SDK2.0.
I didn't have any problem so far with SDK2.0, other peripheral drivers like UART, Ethernet, FTM, ADC do work with interrupt enabled .
