K24 SPI 2 instance using Edma in KSDK 1.3.0

[gsosnow]

I'm using Kinetis MK24FN1M0CAJ12R with KDS 3.0.0 and KSDK 1.3.0 on a custom board.

I've tried to use the DSPI EDMA version of the driver for SPI instance 2, but am getting incorrect SPI transactions on the SPI bus.

However, if I use the DSPI driver without EDMA on SPI instance 2 the transactions are correct.

Furthermore, if I use the DSPI EDMA version of the driver for SPI instance 0, the transactions are correct.

Finally, I have found this errata for the k64 (of which the k24 is a subset derivative, I believe) http://cache.freescale.com/files/soft_dev_tools/doc/support_info/MQXTWRK64RN.pdf which states that a known issue for MQX 4.1.0 is "Because the DMA TX channel and DMA RX channel for SPI1 and SPI2 are the same, SPI1 and SPI2 do not use the DMA driver."

So my question is does this same errata apply to the KSDK 1.3.0 SPI drivers for SPI1 and SPI2 (i.e., that the EDMA version of the KDSK driver should not be used)?

[EarlOrlando]

Hello George,

The MQX and the KSDK drivers are different. The scenario that you need is supported by KSDK so the issue that you comment is not present in these drivers.

I don't have a MK24FN1M0CAJ12R MCU but I have a TWR-K24F120M which has a MK24FN256VDC12 (both have the same SPI and eDMA modules). I tested the dspi_edma_non_blocking example (C:\Freescale\KSDK_1.3.0\examples\twrk24f120m\driver_examples\dspi\dspi_edma_non_blocking). I only changed the SPI instance to 2 and everything works Ok.

Could you please run that example? It will be useful to discard a hardware problem.

I will be looking forward for your response.

Best regards,

Earl.

[gsosnow]

Hi Earl,

Thanks for the confirmation!!

I am able to use SPI2 with EDMA now.

The key was to make sure the state variables are static/persistent, such as edma_state_t and dspi_edma_master_state_t.

It’d be good to clearly spell out in the API doc which arguments are used for subsequent operation of the driver and should be declared static vs. on the stack.

Some such as dspi_edma_master_user_config_t and dspi_edma_device_t can be allocated on the stack and are only used in the calls they are passed to.

I was having a separate initialization function and these were allocated and then deallocated on the stack, before subsequent calls to DSPI_DRV_EdmaMasterTransferBlocking.

To stress this, in the examples, it may be better to not allocate these in functions/on the stack, but outside statically.

One other issue related to the SPI Edma driver was in terms of switching ChipSelects on a SPI bus between calls to DSPI_DRV_EdmaMasterTransferBlocking if one has more than one device on the same SPI bus.

It wasn’t clear what the expected methodology was supposed to be for accomplishing this, since the DSPI_DRV_EdmaMasterTransferBlocking call doesn’t have any way to specify chip select.

One way I was able to accomplish this, was to set the whichPcs field of dspi_edma_master_state_t for the desired chip select before making the DSPI_DRV_EdmaMasterTransferBlocking call.

One thing I needed to make sure of was when I called DSPI_DRV_EdmaMasterInit, that I specify all chip selects that I will use on the bus. Otherwise, the PCSIS field of SPIx_MCR reg won’t be set correctly, and chip select state won’t be correct when switching, leading to some unintended side effects.

Thanks,

George

[EarlOrlando]

Hello again George,

I reviewed the DSPI driver and I think that you are right. I reported this bug with the development team. I will keep you updated about it.

Thanks so much for contact the Freescale Technical Support.

Best regards,

Earl.

[EarlOrlando]

Hello George,

Thanks for your suggestion. The Kinetis SDK 2.0 DSPI driver already added the PCS select parameter for the transfer API.

status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);

/*! @brief DSPI master/slave transfer structure.*/
typedef struct _dspi_transfer
{
    uint8_t *txData;          /*!< Send buffer. */
    uint8_t *rxData;          /*!< Receive buffer. */
    volatile size_t dataSize; /*!< Transfer bytes. */
    uint32_t
        configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the
                        transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
                        is used for slave.*/
} dspi_transfer_t;

/*! @brief Can use this enum for DSPI master transfer configFlags. */
enum _dspi_transfer_config_flag_for_master
{
    kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */
    kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */
    kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */
    kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */
    kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */
    kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */
    kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */
    kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */
    kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */
    kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */
    kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/
    kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */
    kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
    kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
    kDSPI_MasterPcsContinuous = 1U << 20,      /*!< Is PCS signal continuous. */
    kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Is PCS signal active after last frame transfer.*/
};

Best regards,

Earl.

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