CLOCK and GPIO

[nadine]

Hi,

I'm working with a FRDM-K64K board, and KDS 3.0.1 and KSDK 2.0 environment.

I have not a great experience on this environment, so the question could be

obvious for expert guys.

I need to generate a clock signal and connect it to a GPIO output on the FRDM-K64K board.

This GPIO output will be used as the XCLK signal to a device (an AFE032 Power-Line

Communications AFE), available on an external module.

I plan to use the PIT driver, configure it to the requested frequency and set up the GPIO

in the interrupt function of the PIT.

Do you think there is a better, or simplest solution to do so ?

Thanks for your help,

Best Regards

Nadine,

[xiangjunrong]

Hi, Nadine,

if you want to generate clock signal, I suggest you use FTM module instead of GPIO module. If you use GPIO module to generate clock signal, it is okay, you can use PIT module, which can generate interrupt, in the ISR of PIT, you can toggle a GPIO, the disadvantage is the jitter of the GPIO.

The FTM can generate clock signal without jitter, this is the example of FTM in SDK2.0, hope it can help you.

D:\Freescale\SDK2.0\boards\frdmk64f\demo_apps\bubble

You should change the example, disable the FTM interrupt, because you do not need to change the duty cycle. BEcause the desired clock signbal duty cycle is 50%.

This is the PIT example.

D:\Freescale\SDK2.0\boards\frdmk64f\driver_examples\pit

Hope it can help you.

BR

Xiangjun rong

[nadine]

Hi XiangJun,

Thanks for the answer.

Just ot make sure I understand your answer, I will add more details regarding the configuration I'm using.

In this configuration,  a daugther board is connected to the FRDM-K64F board.

This daughter board has its XCLK (input) signal) connected to the GPIO PTE24 of the FRDM-K64F.

That why, I need to generate a clock signal on the GPIO (output).

In your answer, you write, "The FTM can generate clock signal without jitter", but I do not understand the difference

between using the FTM or the PIT timer to have the GPIO generating the clock signal, in the configuration i'm working with.

Thanks for your feedback,

Best Regards

Nadine

[xiangjunrong · Accepted solution]

Hi, Nadine,

I have checked the PTE24, it is not multiplexed with FTM channel output pin, so you have to use the solution that the PIT module generates interrupt, in the ISR of PIT, you can toggle PTE24 to generate clock signal, of course, the solution is okay. As you know, the latency from generating PIT ISR to executing toggling  GPIO in ISR is somewhat indefinite, which leads to the effect that the clock duty is not 50% exactly, the phenomenon is called jitter. The higher the clock frequency is, the more serious the jitter is.

You can refer to the example to generate clock signal on PTE24.

This is the PIT example.

D:\Freescale\SDK2.0\boards\frdmk64f\driver_examples\pit

BR

XiangJun Rong

[nadine]

Hi XiangJun

Thank you very much for your help on this topic.

The best solution would have been to use a PTx multiplexed to a FTM channel.

I will talk with the hardware guys and see if a change can be made.

B.R

Nadine,