CAN issues on S32K146

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

CAN issues on S32K146

1,025 Views
sudeendra_s
Contributor I

Hi

CAN communication development on S32K146 microcontroller and facing below issues.

Could you please help us in resolving these.

 

1) After transmission, not able to see respective buffer bit set in IFLAG1 register indicating successful transmission.

We are able to receive the sent 8byte data in CAN2.0B on receiving node.

How to check successful transmission happened on transmitting node?

 

2) Within how much time successful transmission should happen. For what timeout should CPU wait polling the IFLAG1 register for respective buffer bit?

 

Regards

Sudeendra A

0 Kudos
Reply
1 Reply

919 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

1) if the message is successfully transmitted without errors, the MB flag is always set at the end of the frame, once EOF is detected. Also the CODE field is changing its value, commonly from 0xC to 0x8.
So check if there is no error detected during message transmission. See if CODE field was changed. If yes, check if the flag can be involuntary cleared by SW, using bit access to clearing flags. 
 

2) this is not specified I think. The message is send after the MB wins internal arbitration and on the first opportunity window on the bus (when module sees bus free). If no errors are detected during transmission then the flag is set on EOF detected.

BR, Petr

0 Kudos
Reply