working ddr controller example for k70

[drscott]

Does anyone have a working k70 ddr code example that initializes the ddr memory controller on the k70 tower board and exercises the memory?

drjo

[LANCO_M4]

MQX 3.8 BSP initializes the DDR controller for the DDR2.

Here is the function from MQX that does the work:

/*FUNCTION*---------------------------------------------------------------------
*
* Function Name    : _bsp_ddr2_setup
* Returned Value   :
* Comments         :
*    SDRAM initailization routine.
*
*END*-------------------------------------------------------------------------*/
void _bsp_ddr2_setup (void)
{
    SIM_MemMapPtr   sim = SIM_BASE_PTR;
    DDR_MemMapPtr   ddr = DDR_BASE_PTR;
    MCM_MemMapPtr   mcm = MCM_BASE_PTR;

    /* Enable DDR controller clock */
    sim->SCGC3 |= SIM_SCGC3_DDR_MASK;
   
    /* Enable DDR pads and set slew rate */
    sim->MCR |= 0xC4;   /* bits were left out of the manual so there isn't a macro right now */

    ddr->RCR |= DDR_RCR_RST_MASK;

    * (vuint_32 *)(0x400Ae1ac) = 0x01030203;

    /* TC's init */
    ddr->CR00 = 0x00000400;
    ddr->CR02 = 0x02000031;
    ddr->CR03 = 0x02020506;
    ddr->CR04 = 0x06090202;
    ddr->CR05 = 0x02020302;
    ddr->CR06 = 0x02904002;
    ddr->CR07 = 0x01000303;
    ddr->CR08 = 0x05030201;
    ddr->CR09 = 0x020000c8;
    ddr->CR10 = 0x03003207;
    ddr->CR11 = 0x01000000;
    ddr->CR12 = 0x04920031;
    ddr->CR13 = 0x00000005;
    ddr->CR14 = 0x00C80002;
    ddr->CR15 = 0x00000032;
    ddr->CR16 = 0x00000001;
    ddr->CR20 = 0x00030300;
    ddr->CR21 = 0x00040232;
    ddr->CR22 = 0x00000000;
    ddr->CR23 = 0x00040302;
    ddr->CR25 = 0x0A010201;
    ddr->CR26 = 0x0101FFFF;
    ddr->CR27 = 0x01010101;
    ddr->CR28 = 0x00000003;
    ddr->CR29 = 0x00000000;
    ddr->CR30 = 0x00000001;
    ddr->CR34 = 0x02020101;
    ddr->CR36 = 0x01010201;
    ddr->CR37 = 0x00000200;
    ddr->CR38 = 0x00200000;
    ddr->CR39 = 0x01010020;
    ddr->CR40 = 0x00002000;
    ddr->CR41 = 0x01010020;
    ddr->CR42 = 0x00002000;
    ddr->CR43 = 0x01010020;
    ddr->CR44 = 0x00000000;
    ddr->CR45 = 0x03030303;
    ddr->CR46 = 0x02006401;
    ddr->CR47 = 0x01020202;
    ddr->CR48 = 0x01010064;
    ddr->CR49 = 0x00020101;
    ddr->CR50 = 0x00000064;
    ddr->CR52 = 0x02000602;
    ddr->CR53 = 0x03c80000;
    ddr->CR53 = 0x03c803c8;
    ddr->CR53 = 0x03c803c8;
    ddr->CR56 = 0x020303c8;
    ddr->CR57 = 0x01010002;

    _ASM_NOP();

    ddr->CR00 |= 0x00000001;

    while ((ddr->CR30 & 0x400) != 0x400) {
    }

    mcm->CR |= MCM_CR_DDRSIZE(1); 
}

[drscott]

Thanks LANCO.  I did have the DDR setup routine in my Crossworks project with the freescale sysinit.c program compiled in.  However, I did not have the DDR_INIT defined in my project so the twr_ddr2_script_init() routine was never called.  I also defined SYNCH_MODE in my project; I am not sure how critical the SYNCH_MODE define is to the overall workings of the ddr controller???  In any case, I did get the ddr controller working and exercised it with the attached memtest.c program.  Both the 

memTestDataBus(volatile datum * address) and the memTestAddressBus(volatile datum * baseAddress, unsigned long nBytes) routines work fine.  The memTestAddressBus utility takes several seconds to run through all ddr memory.  The memory testing setup stuff is included here:

datum * myptr;
volatile datum * baseAddress;

unsigned long nBytes;

//test memory bus...
baseAddress = 0x80000000;
nBytes = 0x8000000;
printf("Starting ddr mem testing...\n");
myptr = memTestAddressBus(baseAddress, nBytes);

if(myptr != NULL)
{
printf("memory testing failed...\n");
}
else
{
printf("memory testing okay...\n");
}

baseAddress = 0x80000000;
nBytes = 0x8000000; //

printf("memory fullscale testing started...\n");
myptr = memTestDevice(baseAddress,nBytes);
if(myptr != NULL)
{
printf("memory testing failed at loc %x\n",myptr);
}
else
{
printf("full scale memory testing okay...\n");
}

[LANCO_M4]

I am not sure about the SYNCH_MODE directive. I havent seen this one. Where is it located?

We are using CW10.x here and MQX 3.8 and have had the DDR2 working on the Tower K70 from the start. We are having issues with our board which is using DDR1. It is really a strange problem where the board (ddr or display controller) doesn't work correctly if the debugger is not connected. It seem that the JTAG / Debug port needs to be active other wise the data from the LCD frame buffer that is located in the DDR is not read correctly.

[ColoPaul]

Hi drscott and LANCO_M4.

  We are using a Tower K70 / DDR2;  and I have two questions for you.

  1)  In the MQX init code (same as what you posted):

    ddr->CR52 = 0x02000602;
    ddr->CR53 = 0x03c80000;
    ddr->CR53 = 0x03c803c8;
    ddr->CR53 = 0x03c803c8;
    ddr->CR56 = 0x020303c8;
 

 There appears to be a typo, should be CR53, CR54, CR55;    I've talked to the MQX developer, who got the code from Freescale.  He polled someone at freescale about it but did not get a response.   Do either of you know enough about DDR2 to know what should be going on in the init code?

   We have tried it both ways and the DDR2 on the tower seems to work OK either way.

  2) We are experiencing all kinds of issues with DMA between peripherals & DDR2.   DMA works perfectly with internal SRAM & periphs.   Have you any experience with this?

Thanks, Paul

[LANCO_M4]

Yes it looks like that isnt correct. I just posted what was in the MQX BSP for the K70.  I know that the DDR2 setup on the tower apeared to be working with this code.

On our board, which uses DDR1, we used a DDR utility given to us by Freescale to generate the configuration. We did have an issue had to add the following line to get our DDR working.

SIM_MCR |= 0x00000008;

We are using the DDR to hold the LCD frame buffer and everything apears to be working OK.

[DamonGibson]

Did the K70 DDR Configuration Utility ever get published on the Freescale web site?  If so, does anyone know where to find it?  I did not see it in the MQX 4.2 or CodeWarrior 10.6 distributions.

Thanks,

[alipoth]

Hi John,

Is the DDR utility the same as the QorIQ Configuration Suite or do I need a separate tool for Kinetis?

Cheers,

Andras

[alipoth]

Answering my own question: the QorIQ tools doesn't support Kinetis. For K70 memory configuration tool one has to contact Freescale, as it can not be downloaded directly from the public website.

[drscott]

ColoPaul,

I am getting back to our k70 ddr work and want to give you an update.  First off, the three ddr->CR53 duplicates that you highlight should indeed be CR53, CR54, and CR55 as you suggested - this is based on my current (incomplete) knowledge of the ddr controller.  We have consideralble experience programmatically reading and writing to ddr memory - all experiences to date are positive.  We have not done any DMA's to sdram memory as of yet so I cannot comment on that.  We are reading high-speed spi data and using the sdram as large buffer space and this works fine.  However, when we are try to load application code into the ddr memory space and do absolute address calls into these ddr memory-based  routines, we are getting nothing but hardware faults.  I don't know if our issues are related to your DMA issues but I would guess that they are.  I don't see anthing that I should be setting up to explicitly allow program execution (or DMA access) into ddr memory - a cursory read of how the MMU works and is set up (in default) doesn't shed any light on this issue.  Can you or anyone else give some guidance?