watchdog program S9KEAZ128AMLH

[joopaandentoorn]

Hi,

I am trying to get the watchdog to work on an S9KEAZ128AMLH chip, running it from bare metal. The user manual states that the watchdog can be refreshed upon writing the following sequence to WDOG registers CNTH:CNTL

0x02A6

0x80B4

However, if I try this the chip resets immediately. I have also tried swapping the values (i.e. 0xA602 and 0xB480) with a 16-bit write, and even writing the CNTH and CNTL registers separately with those combinations. Same story when I try to unlock the chip with sequence (tried swapping the big/little endian order on those too)

0x20C5

0x28D9

To at least be able to work with the chip, I dived into the S32 IDE automatically generated code and blindly applied the code I found there to my own project:

#if (DISABLE_WDOG)

  /* WDOG->TOVAL: TOVAL=0xE803 */

  WDOG->TOVAL = WDOG_TOVAL_TOVAL(0xE803); /* Timeout value */

  /* WDOG->CS2: WIN=0,FLG=0,??=0,PRES=0,??=0,??=0,CLK=1 */

  WDOG->CS2 = WDOG_CS2_CLK(0x01);       /* 1-kHz clock source */

  /* WDOG->CS1: EN=0,INT=0,UPDATE=1,TST=0,DBG=0,WAIT=1,STOP=1 */

  WDOG->CS1 = WDOG_CS1_UPDATE_MASK |

             WDOG_CS1_TST(0x00) |

             WDOG_CS1_WAIT_MASK |

             WDOG_CS1_STOP_MASK;

#endif /* (DISABLE_WDOG) */

I quickly learned that I could succesfully write to the control registers CS2 and CS1, after writing any random value to TOVAL. If I omit writing to TOVAL, the chip is reset immediately upon writing to CS2 or CS1. What is going on here? I believe the datasheet is either incomplete or incorrect but I need the watchdog function. What are the actual refreshing codes and how do I unlock the chip? What other settings on the chip can influence the watchdog? Am I doing something really wrong?

[kerryzhou]

Hi Joop aan den Toorn,

       Attached is the KEA watchdog driver code, you can refer to this code.

      After reset, you should call WDOG_DisableWDOGEnableUpdate() function at first, because after reset, the WDOG_CS1[UPDATE] is 0, it is not allowed to do updates, you need to enable it at first, besides this bit is the write once bit after rest, then you should set it at first after the MCU reset.

Wish it helps you!

If you still have question, please let me know!

Have a great day,
Jingjing

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[joopaandentoorn]

I have solved the problem. I think the GCC compiler tries to optimize the 16-bit writes to 32-bit as much as possible. If anybody else has this problem, I used the following code to succesfully refresh the watchdog:

	uint16_t * cntAddr =  (void * ) &WDOG_HW->CNTH;
	*cntAddr = (uint16_t) 0x02A6;
	*cntAddr = (uint16_t) 0x80B4;

Declaring the CNT register as a 16-bit unsiged integer and updating it did not work for me somehow.

By the way, I have noticed the following behavior

- I have to write the refresh sequence as a 16 bit write to CNT. The first unlock part (0x02A6) can actually be written to CNTH and CNTL in two successive 8-bit writes, but if I do that for the second unlock step, the watchdog forces a reset (order of writing to CNTH and CNTL does not matter). Why is that?

i.e. this works:

		WDOG_CNTH = 0xA6;
		WDOG_CNTL = 0x02;
		WDOG->CNT = 0x80B4;

this does not:

		WDOG_CNTH = 0xA6;
		WDOG_CNTL = 0x02;

		WDOG_CNTL = 0x80;
		WDOG_CNTH = 0xB4;

how come?

[kerryzhou]

Hi Joop aan den Toorn,

     I think it is caused by the time limit, because according to the RM:

The write of the 0x80B4 must occur within 16 bus clocks after the write of 0x02A6; otherwise, the watchdog resets the MCU.

    When you write the 0X80B4 in 8 bit mode, the code :

	WDOG_CNTL = 0x80;
		WDOG_CNTH = 0xB4;

may larger than 16 bus clock, you can check the asm code, to calculate the code execution time, whether it is larger than 16 bus clock.

Wish it helps you!

Have a great day,
Jingjing

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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[joopaandentoorn]

By the way, I have tried to use the refresh codes after 150 bus cycles delay of writing to CS1. This sends the chip into a reset. Through software debugging I was able to verify the watchdog works fine otherwise. Whatever I write to CS1 and 2 works like it should, but still no luck on refreshing the counter.