monitoring eDMA activity in hardware

[lenshustek]

I'm using eDMA on a K66 to read data samples from external hardware at a pretty fast rate. The hardware generates a transfer request pulse, which I wired to one of the data port inputs and use its falling edge to trigger the DMA request .That works well.

But I would like to add some hardware to detect if ever the eDMA wasn't able to service a request in time before the next request arrives. Is there any way to configure an external hardware output that indicates when a DMA channel is serviced? It's happening too fast to monitor in software.

[mjbcswitzerland]

Len

You can use a second eDMA channel to use the GPIO trigger to write a value to a GPIO toggle register. Like this it will cause an output to change state on each trigger.

There are however three things to be aware of:

1. Although it works to trigger 2 DMA channels from the same port it is not recommended in the user guides (it would need the same signal connected in parallel to two different ones to be "clean").
2. This doesn't prove that the other channel is actually operating since it may be that the other channel has stalled due to some reason.

3. Don't underestimate the extra bus load due to continuous fast DMA. I have seen Ethernet and USB start to overflow due to other DMA operations slowing access overall - and the processor instruction core ill also be waiting more for the bus.

Assuming that the main channel would only stop due to some form of error you can also use the eDMA error interrupt to display that something is wrong. You could then have a free running timer output showing is is well and stop it if the eDAM error interrupt fires (if a toggling signal is to indicate OK).

In software you could also periodically check the eDMA counter - if you poll it (slowly) and see that it hasn't changed there is possibly something wrong. The reaction time to detecting an anomaly would however be determined by the polling rate.

Regards

Mark

[lenshustek]

A clever idea, thanks! But I'd hate to run another DMA channel in parallel that creates an additional bus load for every incoming data sample. As it is, as data buffers are filled (using scatter/gather) by the first DMA channel reading from the external hardware, I'm running a second DMA process that exports the data. So in steady state there are already two DMA operations per sample.

I'm not so worried about the DMA stopping altogether because of an error; I'll be able to detect that. I'm more worried that temporary bus overload will cause a single sample to be missed because the DMA request wasn't serviced before the next sample arrived. I suppose I could add an external hardware counter and compare how many transfer requests it saw to what the eDMA channel processed over some time period, but that's a lot of extra chips and has some tricky start/stop issues because the data is continuously flowing.