clarify VLLS[2,3] wakeup through reset on cortex m0+

[biosbob]

when i wakeup from VLLS[2,3] mode, documentation says i wakeup through "reset"; by contract LLSx the wakeup is through the "WFI" instruction....

in my cortex m0+ application, i've actually MOVED SCB->VTOR to an address other than 0x00000000 (for reasons beyond the scope of this question)....

it appears that (despite moving the VTOR) the "reset" wakeup goes back through the original vector at address 0x00000000....  is that by design????  or is there someway to have the wakeup "reset" go through the vectors currently referenced by the VTOR register????

[biosbob]

in my case, i do have my own bootloader at 0x0....  but care has to be taken when writing your own bootloader to handle a "wakeup reset" and not (for example) initialize memory!!!!

[Daniel-Aguirre · Accepted solution]

Hi,

As for design goes, when a RESET is issued, the Program Counter (or PC) goes to a reset state, which normally is 0x0 (or the origin). This is by design and, to my knowledge, this is core related and you cannot modify this reset value.

What you could do is send from 0x0 to whatever address or table you need. If you are working with a system with built-in bootloader, just verify the flow of the program, some interrupts cannot be modified by user as they are defined by design and are platform related.

Let us know if this helps you or not.