What is the maximum number of interrupts that can be handled per second in a kinetis K61 (MK61FX512VMJ15) controller

[sumitnandi]

Hi Everyone

I want ADC (single conversion) samples every 72usec. In my project i already have 1ms timer interrupts and UART interrupts at every 5ms or so and few other interrupts as well. I am not using DMA. ADC is triggered through PDB.

SIM_SCGC3 |= (SIM_SCGC3_ADC1_MASK);

ADC1_CFG1 = ADC_CFG1_MODE(0x02) | ADC_CFG1_ADICLK(0x01);

ADC1_CFG2 = ADC_CFG2_ADHSC_MASK;

ADC1_SC2 = ADC_SC2_ADTRG_MASK ;

ADC1_SC3 = ADC_SC3_CALF_MASK;

My problem:  with ADC samples every 500usec and all other interrupts am getting expected behavior and halts at breakpoint in ADC interrupt routine. But when i change this period to less than 500 usec i.e 400usec or 300usec the observed behavior is unexpected; there are no halts in ADC interrupt routine.

I am suspecting that below 500usec period a large number of interrupts are being generated which is causing miss in servicing interrupts.

Would using DMA help me in capturing all the ADC samples?

Thanks

[xiangjun_rong]

Hi, Sumit,

As far as I know that the K61 core/system clock frequency can reach up 120mhz or 150mHz, depending on the derivative. I think it is okay to sample ADC in 3KSPS with interrupt mechanism.

I suggest you write the ISR as simple as possible. Regarding your ADC sampling, I suppose you use PIT or PDB to trigger ADC, in the ISR of ADC, you need just read the sample from ADC result register and write the sample to an array, set a flag. In the loop  in main.c, you can deal with the sample based on the application after the flag is set.

Hope it can help you

BR

XiangJun Rong

[sumitnandi]

Hi XiangJun

Thanks for your response. I have already implemented the way you mentioned. The problem persists. Keeping PDB trigger so as to get more than 2KSPS ADC I am not able to get a #halt on my breakpoint in ISR. If i sample ADC at 2KSPS and below i get halts at my breakpoint in ISR. I am using Segger J-Link Plus debugger.

My project(legacy) is MQX RTOS based. Further, in my project the 1ms timer ISR is long and having 4-5 levels of function calls. My code is in C/C++.

3KSPS is my minimum requirement. My best case requirement is 12KSPS ADC

Would you recommend to go for DMA in this case?

I searched forum and got this thread---can i draw some conclusions from this?-->Achieving max ADC sampling rate on the K60 

[xiangjun_rong]

Hi,

Maybe this is the debugger issue. I suggest you toggle an GPIO in ADC ISR, use scope to observe the GPIO signal, if the GPIO signal frequency is the same as PDB triggering frequency,and the sample value is correct, it is okay. You can also toggle a GPIO in main loop to check the core profile.

I think it is okay to use DMA to read ADC sample to memory to save core load.

BR

Xiangjun Rong