The data sheet for the K32L never gives a clear source for where the TSTMR clock comes from.
What follows are the various reference related to TSTMR scattered through the Reference Manual.
Anyone have answer?
" The TSTMR runs off the 1 MHz clock and resets on every system reset."
| TSTMR | SIRCLK @ 1 MHz |
| Chip Reset DIVSLOW_CLK |
" In addition to the run mode when the device resets, the DIVCORE_CLK divide ratio is
determined by the NVM (IFR) options. The IFR bits set the DIVCORE field in the
SCG’s Run Clock Control Register (SCG_RCCR). Similarly the DIVSLOW_CLK divide
ratio is also determined by the NVM (IFR) options.
Out of reset, the SIRC module is enabled and used as the main clock source out of reset.
This provides an 8MHz source clock "
By default DIVCORE_CLK is divide by 1, DIVSLOW_CLK is divide by 2, giving 4 MHz at reset. Is there a divide by 4 in the TSTMR to get 1 MHz?
fsl_tstmr.h implies that the clock can be 1 MHz or 8 MHz:
/*!
* @brief Delays for a specified number of microseconds.
*
* This function repeatedly reads the timestamp register and waits for the user-specified
* delay value.
*
* @param base TSTMR peripheral base address.
* @param delayInUs Delay value in microseconds.
*/
static inline void TSTMR_DelayUs(TSTMR_Type *base, uint32_t delayInUs)
{
uint64_t startTime = TSTMR_ReadTimeStamp(base);
#if defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ) && FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ
while (TSTMR_ReadTimeStamp(base) - startTime < delayInUs)
#elif defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ) && FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ
while (TSTMR_ReadTimeStamp(base) - startTime < 8 * delayInUs)
#else
assert(0);
#endif
{
}
}
