What is the clock source for TSTMR in the K32L2A?

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

What is the clock source for TSTMR in the K32L2A?

ソリューションへジャンプ
1,219件の閲覧回数
bobpaddock
Senior Contributor III

The data sheet for the K32L never gives a clear source for where the TSTMR clock comes from.
What follows are the various reference related to TSTMR scattered through the Reference Manual.

Anyone have answer?


" The TSTMR runs off the 1 MHz clock and resets on every system reset."

TSTMRSIRCLK @ 1 MHz
Chip Reset DIVSLOW_CLK


" In addition to the run mode when the device resets, the DIVCORE_CLK divide ratio is
determined by the NVM (IFR) options. The IFR bits set the DIVCORE field in the
SCG’s Run Clock Control Register (SCG_RCCR). Similarly the DIVSLOW_CLK divide
ratio is also determined by the NVM (IFR) options.

Out of reset, the SIRC module is enabled and used as the main clock source out of reset.
This provides an 8MHz source clock
 "

By default DIVCORE_CLK is divide by 1, DIVSLOW_CLK is divide by 2, giving 4 MHz at reset.  Is there a divide by 4 in the TSTMR to get 1 MHz?


fsl_tstmr.h implies that the clock can be 1 MHz or 8 MHz:

/*!

* @brief Delays for a specified number of microseconds.
*
* This function repeatedly reads the timestamp register and waits for the user-specified
* delay value.
*
* @param base TSTMR peripheral base address.
* @param delayInUs Delay value in microseconds.
*/
static inline void TSTMR_DelayUs(TSTMR_Type *base, uint32_t delayInUs)
{
uint64_t startTime = TSTMR_ReadTimeStamp(base);

#if defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ) && FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_1MHZ

while (TSTMR_ReadTimeStamp(base) - startTime < delayInUs)

#elif defined(FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ) && FSL_FEATURE_TSTMR_CLOCK_FREQUENCY_8MHZ

while (TSTMR_ReadTimeStamp(base) - startTime < 8 * delayInUs)

#else

assert(0);

#endif
{
}
}

0 件の賞賛
返信
1 解決策
1,166件の閲覧回数
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi bobpaddock,

Sorry for the inconvenience we bring you!

It is confirmed that there is a 1MHz output from the SIRC that runs whenever the SIRC is enabled and is used to clock the TSTMR.

Best Regards,
Robin

元の投稿で解決策を見る

0 件の賞賛
返信
2 返答(返信)
1,167件の閲覧回数
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi bobpaddock,

Sorry for the inconvenience we bring you!

It is confirmed that there is a 1MHz output from the SIRC that runs whenever the SIRC is enabled and is used to clock the TSTMR.

Best Regards,
Robin

0 件の賞賛
返信
1,162件の閲覧回数
bobpaddock
Senior Contributor III

Thank you.

 

0 件の賞賛
返信