I think we will classify this under 'general knowledge'. That is, ANY digital-function device will list the voltage above which an input is GUARANTEED to be sensed as a logic '1', and another voltage below which it is GUARANTEED to be sensed as a logic '0', and 'between those' is a no-man's-land for which the forwarded logic-level is indeterminate. Now these parts have hysteresis on the inputs, so at least a 'mid voltage input' will not bounce around and do 'silly things', but (to use your 5V example) any voltage between 1.75V and 3.25V CANNOT be expected to resolve as 'any particular' logic level (and, as I also mentioned, will result in increased input-stage current). 'In general' you can 'expect' the P and N FETs of a CMOS input stage to be 'fairly well balanced', and thus to switch 'very near 1/2 Vdd'. This 'datasheet margin' (+/-0.75V on your 5V example) is there to allow some imbalance to exist over a range of parts and pins (and thus tolerance for the manufacturing variables such as those defining circuit element dimensions and 'transistor doping' levels), yet give a circuit designer 'known limits' to work within.
Even if you 'measure' a particular part&pin 'switch point' at some particular temperature, you MUST expect that 'switch point' to be different for other parts/pins/temps, anywhere within the 'guaranteed limits' of the datasheet.
If you need ANY kind of 'assured switching points', you need to use 'real' comparator(s), either internal or external, which give 'much tighter' switch-points against some reference voltage (at the expense of being slower analog circuits, of course!).
