What are differences within K60 series and how does it affect programming

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What are differences within K60 series and how does it affect programming

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BryanCrosby
Contributor II

We are developing a new application using K60 chip.

Intially our development was slow and used the MK60DN512VLQ10 , but now as we are interested in floating point calculations and the extra memory we are considering the MK60FN1M0VLQ12. The 120 chip has more memory and FP processor and otherwise the same number of pins.

Are there significant programming changes to get the DN512 code working on the FN1M0V.

Obviously RAM is more plentiful, expect minimal problem there.

But the I/O assignment, will that be pin compatible ?

Any other issues that people know about or anticipate ?

1 Solution
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deepakrana
NXP Employee
NXP Employee

Hi

Below are the answers

1. your clocking structure will change, you will have two PLL and the input range to PLL will be from 4 -8 Mhz. With FLL the max frequency you can generate will be 100Mhz. This you need not worry our code takes care if you are using them for drivers. The extra PLL is for the DRAM controller that you will get with it.

2. you will have instruction and data cache

3. The page size/sector size for 120 Mhz    will be 4K

4. If you upgrade in the same package , most likely the part will be drop in , but you will need to manually need to check for additional power pins or peripheral specific pins.

5. Since the pheripheral remains same you will be good with the rest. Don't forsee any other issues.

6. For FP unit you need to use the CMSIS library . Web-link:

Tutorial: Using the ARM CMSIS Library | MCU on Eclipse

Advisable to use the gcc compiler(within CW) for your development as this will integrate well. If you are on IAR then this step you can ignore.

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147 Views
deepakrana
NXP Employee
NXP Employee

Hi

Below are the answers

1. your clocking structure will change, you will have two PLL and the input range to PLL will be from 4 -8 Mhz. With FLL the max frequency you can generate will be 100Mhz. This you need not worry our code takes care if you are using them for drivers. The extra PLL is for the DRAM controller that you will get with it.

2. you will have instruction and data cache

3. The page size/sector size for 120 Mhz    will be 4K

4. If you upgrade in the same package , most likely the part will be drop in , but you will need to manually need to check for additional power pins or peripheral specific pins.

5. Since the pheripheral remains same you will be good with the rest. Don't forsee any other issues.

6. For FP unit you need to use the CMSIS library . Web-link:

Tutorial: Using the ARM CMSIS Library | MCU on Eclipse

Advisable to use the gcc compiler(within CW) for your development as this will integrate well. If you are on IAR then this step you can ignore.

View solution in original post

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146 Views
deepakrana
NXP Employee
NXP Employee

hope this helped with the clarifications that you sought