Valid Clock Frequencies for K32 ADC

[aberger]

I'm trying to understand the effect of the ADC CFG2[ADHSC] (High-Speed Configuration bit) for the K32. Supposedly it configures the ADC for very high-speed operation, but it always adds two addition ADCK cycles to the total conversion time.

Judging from the data sheet, one must set ADHSC = 1 to use the maximum ADC conversion clock frequencies. What frequencies require this? What are the range of valid clock frequencies if ADHSC = 0?

Additionally, what is the impact of ADLPC (Low-Power Configuration)? What are the range of valid clock frequencies if ADLPC = 1?

The data sheet only lists minimum and maximum clock frequencies, but not the range of valid frequencies for a given configuration.

[xiangjun_rong]

Hi,

I suppose that you use K32L2 family, this is the ADC block diagram, from the diagram, you can see that the ADC clock ADCK can be from 4 sources:ADCACK(fADCACK ADC asynchronous clock source), Bus clock, divided2 bus clock, ALTCLK.

If you want to get the highest conversion rate, you have to select Bus clock, which can reach up to 24mhz, the ADC conversion rate can reach up to 1.2MBPS.

This is the table using bus clock:

If you want to get the normal conversion rate, you can select asynchronous clock ADACK, which can reach up to 6.2mhz typically, when ADLPC=0, ADHSC=1.

This is ADC block diagram.

For the detailed conversion rate computation, pls refer to 23.5.4.5 Sample time and total conversion time in K32L2B3xRM.pdf

Hope it can help you

BR

XiangJun Rong

[aberger]

Judging by table 57 from the datasheet, it appears that ADHSC only affects the achievable clock frequencies when using the Async Clock. Is that correct? (Though it always adds 2 cycles if enabled, regardless of clock source?)

[xiangjun_rong]

Hi,

Yes, when you set the ADHSC bit,two more ADCK cycles are required to convert one analog channel.

Hope it can help you

BR

XiangJun Rong

[aberger]

Yes, I understand the additional 2 clock cycle penalty. But is there any reason to use ADHSC if not using the Async Clock? For example, if using the Bus Clock, using "High-Speed Configuration" seems to simply slow down conversion by adding two clock cycles, and has no impact on the actual clock speed. Is that correct? If so, even though called "High-Speed Configuration", it actually slows things down. The documentation is frustratingly unclear about this point.

[xiangjun_rong]

Hi,

If you want to get high conversion rate for ADC of K32L2 family, you have to use BUS clock, the ADCK clock must be less than 24Mhz, the ADCK clock is the output of the ADC clock divider, while you have to set the ADHSC bit and clear the ADLPC bit.

The high speed mode is enabled by setting the ADC_CFG2[ADGSC], the ADC high speed mode is a mechanism of ADC conversion.

Hope it can help you

BR

Xiangjun rong

[aberger]

Now I see in footnote (5) of Table 56 that ADHSC maybe does apply even when using a clock source other than the Asynchronous Clock ADACK.

I also see in the reference manual:

CFG2[ADHSC] must be used when the ADCLK exceeds the limit for CFG2[ADHSC]=0.

Are these limits published anywhere? In Table 56, it lists the minimum and maximum f_ADCK, but it doesn't describe what the limiting case for ADHSC = 0 is.

For example, with ADICLK = BUS Clock (24 MHz), and divisor = 2, the ADCK is 12 MHz. This is at the maximum for 16-bit conversions, so I assume this requires ADHSC = 1 . Is that correct?

With divisor = 4, the ADCK = 6 MHz, which is in between the minimum and maximum f_ADCK for 16-bit conversions. Is this achievable with ADHSC = 0?

[xiangjun_rong]

Hi,

For the ADC of K32L2 family, the UM is unclear about the high speed and low speed ADC clock frequency.

This is an internal table for the ADC setting.

Hope it can help you

BR

XiangJun Rong