Using PWM to request DMA for next PWM value

[davedanenberg]

The problem…

I don’t have exact values, but with my system’s K10 clock speeds (Core 72m, PWM 750k), when the PWM duty cycle is set below ~80%, the DMA/PWM appears to work correctly. Then somewhere greater than 80%, the FTM’s DMA request does not get serviced in time for its next reload. Based on my observations, it looks like the DMA request for the next PWM value is sent at the falling edge (FTM comparator) of the PWM – and then pending (ie, double buffered) PWM values are reloaded at the rising edge (FTM reload). What I see is if the time between the falling and rising edges is too short, then the PWM’s new value arrival (via DMA) is not in time for the reload. In this case, the new PWM value appears one FTM cycle later.

Question…

What I am wondering is if there is a formula that will describe when the FTM’s DMA request must be asserted to guarantee the next PWM value arrives before the FTM reload. Perhaps this (hypothetical) formula is based on Core clock and PWM rate.

Thanks

-Dave

[xiangjun_rong]

Hi, Dave,

Regarding your question that the DMA can not update the PWM duty cycle reliably, I think we should find out the other solution, as Mr Josh said, it is not reliable just to write the FTM_CnV register by DMA from a variable from memory in order to update the duty cycle of PWM..

If you would like to write the FTM_CnV register to update the duty cycle reliably, I suggest you you use the FTM loading function by set the LDOK bit in FTM_PWMLOAD, in the method, the DMA has to write FTM_CnV register even FTM_Cn+1V, FTM_Cn+2V... registers and FTM_PWMLOAD, so the DMA needs complicated configuration, but I think the method is feasible. You can use minor channel link mode of DMA, for example, after  FTM_Cn+1V, FTM_Cn+2V... register has transferred by DMA, the minor channel link is triggered, then the linked channel of DMA can transfer the data in  a variable to FTM_PWMLOAD to set the LDOK bit, I think the PWM duty cycle can be updated reliably in this way.

If you are familiar with eDMA module, you can have a try. I think the solution is feasible, but I have never tried yet, I will develop an example to try the method.

Hope it can give you clue.

BR

XiangJun Rong

[davedanenberg]

Josh/XiangJun,

Thanks for your thoughts. I will certainly look into this, and will appreciate any new methods you may develop. Currently I have 1 dedicated DMA channel for each PWM (FTM channel) I'm running, but for the sake of discussion, let's just talk about updating 1 value (FTM_CnV). Interesting about the linked DMA channels. I am reading about the LDOK bit, I am not sure it will do what I want (that is, guarantee when the new CnV value gets loaded).

Note - my application is running through a fixed length table (128 entries) each table entry can have a different (match) value to load into the PWM - and each of the 128 values needs to be loaded sequentially for every subsequent PWM cycle. Then the table repeats (modulo 128). I have this all running OK - except for noticing the (approx) 80% mark (when the match is 80% of the mod) where the next PWM value load can be delayed by 1 cycle. What I really want is an FTM config bit that says "Send the DMA request at FTM MOD time, not at FTM match time", but this probably does not exist.

Thank you

-Dave

[xiangjun_rong]

Hi, Dave,

I developed the example code with TWR-K40x256 based on the thought that the FTM_CnV matching triggering DMA, DMA use one channel to transfer data in an array to update the FTM_CnV to update the duty cycle of PWM, while minor link channel is triggered  to write the PWM_PWMLOAD register to set the LDOK bit, I use edge-alignment mode, it seems that it is okay. But the FTM_CnV can not be set up as zero, if the FTM_CnV is set up as zero,  triggering signal from FTM seems seems  not to generate, in other words, no triggering.

Hope it can help you.

BR

Xiangjun Rong

[davedanenberg]

Xiangjun ,

There is a problem extracting your attached file. "Unexpected end of archive". Also, if I look through the extracted file, I don't see any source code - other than code that seems to be auto-generated. Looks like most of the project files are there - I am able to import the project into KDS, but I don't see any PWM/DMA code.

Regards,

-Dave

[xiangjun_rong]

Hi,Dave,

sorry for the delay, I was out of office in the last week.

I attach the example code here.

BR

XiangJun Rong

[joakimarnsby]

Hi!

I'm also trying to use DMA to load the FTM with values, I'm using center aligned pwm mode.

I have set it up as in your example, FTM-DMARQ -> DMACH0 -> Minor link-> DMACH1

DMACH0 moves data to FTM0_C0V and then triggers DMACH1 to set the pwm load bit.

The problem I have is that it apperas that I get two DMA requests per period from the FTM timer, only every other value from my buffer gets used.

When I set the Major loop to 16 iterations it ends after 8 pwm periods.

Is there a way to get around this?

BR

Joakim

[robotjosh]

What are you trying to do with dma and pwm?  Maybe there is another more reliable way to do it.  I have had a lot of trouble getting pwm dma to work.  I have seen it work differently on different chips.  For instance, on some chips a zero duty cycle will assert the dma flag and on some chips it wont.  Maybe you could get more reliability with center aligned pwm if it can set the dma flag at the top of the count.