Trigger a DMA transfer - (SPI transfer ) periodically with PIT

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Trigger a DMA transfer - (SPI transfer ) periodically with PIT

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viveknath_thulasi
Contributor II

Hi,

µC - MK66

I am trying to configure a EDMA transfer with SPI and PIT with the peripheral Tool. 

My requirement is , On a GPIO interrupt I need to trigger a PIT(PIT0) which inturn needs to trigger the SPI-EDMA transfer

40 Transfers ( on Each Transfer 4 * 2 Bytes data ) 

So I configured

DMA #60: AlwaysOn 60 - for Tx to SPI1 through eDMA Ch-0

, with Tx to SPI1->PUSHR 

and #16: SPI1 Receive for Rx messages. eDMA Ch-1

with recieve data Rx on SPI1->POPR

I return the Transaction to µC after 40 Transfers (On Major Loop Completion)

are completed to stop the PIT and continue.

On Non-transactional (TCD structure)

Minor Count of 4 

Major Count of 40 

I also configured SPI1 seperately with its configuration

I am not able to see any SPI transfers happening. And Also based on these Peripheral Setting, execution asserts on Initialization DSPI_MasterTransferCreateHandleEDMA   (edmaRxRegToRxDataHandle, edmaTxDataToIntermediaryHandle) 

I am able to get the interrupt and start the PIT

As I need to configure PIT to trigger DMA, I did not enable interrupts on it. 

What am i Missing?

Any info would be helpful.

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1,725 Views
viveknath_thulasi
Contributor II

Hi,

This is exactly what I wanted to do.

 

I am able to get GPIO to trigger PIT . But on PIT expiring, it is not triggering DMA - SPI transfer at edma channel0.

Regards,

Viveknath 

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Pavel_Hernandez
NXP TechSupport
NXP TechSupport

Hello viveknath_thulasi

I recommend you use the example from the SDK, DSPI EDMA B2B and combine this with the PIT example, I made a little test with two boards, but I build this with software trigger with successfully result.

Regards,

Pavel_Hernandez

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Pavel_Hernandez
NXP TechSupport
NXP TechSupport

Hello again I forget something, in the example from the SDK there are a macro TRANSFER_SIZE you can modify to 8U and trigger 40 for each transfer.

Regards,

Pavel_Hernandez

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1,683 Views
viveknath_thulasi
Contributor II

Hi,

Thanks a lot for your response.

Do we have to configure PIT with interrupts? 

Also , Do we have to start the EDMA transfer explicitly? or it is triggered automatically from the PIT software triggers?

 

if Possible can you please share the Test project for reference ?

 

Regards,

Vivek

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Pavel_Hernandez
NXP TechSupport
NXP TechSupport

Hello viveknath_thulasi

Q1) Do we have to configure PIT with interrupts? 
R1) That's right, I recommend review the example PIT form the SDK.

Q2) Do we have to start the EDMA transfer explicitly? or it is triggered automatically from the PIT software triggers?
R2) I found some information may help you in the Reference Manual, please review the chapter 23.1.2 DMA transfers via PIT trigger.

Q3) Possible can you please share the Test project for reference ?
R3) I recommend use the example from the SDK and combine as you need it.

Reference Manual link below.

Kinetis K66: 180MHz Cortex<sub>®</sub>-M4F up to 2MB Flash (144pin) (nxp.com)

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viveknath_thulasi
Contributor II

Hi Pavel Hernandez,

 

Thanks a lot for your response.

I have made some progress with the implementation but not yet fully achieved.

I want to clarify some updates:

1. I am Able to trigger the DMA channels without configuring PIT as interrupts.

2. I have referred this sections section 23.1.2 . It was helpful thank you.

3. the example uses channel API : Transactional structures and I want to use Non - Transactional Structures with much more flexibility to configure minor loop and major loop counts and Modulo operations. 

The important problem that I faced was to provide a particular RAM section for : AT_NONCACHEABLE_SECTION_ALIGN_INIT - This is a part of generated code from the Peripheral tool.

I added a separate RAM section in the Project settings and hence now i am able to access the generated TCD structures.

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Pavel_Hernandez
NXP TechSupport
NXP TechSupport

Hello viveknath_thulasi

In order to help you, I understand the follow, you want to make with an GPIO IRQ trigger the PIT, when the PIT expire the count, trigger the DMA to fill the SPI with data to make the transference. Please correct me if that isn't correct.

Regards 

Pavel_Hernandez

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