TWR-K70 MSD HOST Bootloader : PLL error

[arnogir]

Hello,

I'm using the K70 bootloader found here:

TWR-K70 MSD HOST Bootloader based on AN4368 source code

I have already tested it on the board without any problem.

Now I want re test the boot.

Then I compile, flash with the P&E, all work correctly.

Now I unplug the P&E to Run the board in standalone.

Board do nothing.

If I "Attach" the debugger, code is stay here in the following while(1). Anybody know where can come from my problem?:

in P3.c, _bsp_platform_init

 /* Initialize PLL0 */
 /* PLL0 will be the source for MCG CLKOUT so the core, system, FlexBus, and flash clocks are derived from it */ 
 mcg_clk_hz = pll_init(OSCINIT,   /* Initialize the oscillator circuit */
   OSC_0,     /* Use CLKIN0 as the input clock */
   CLK0_FREQ_HZ,  /* CLKIN0 frequency */
   LOW_POWER,     /* Set the oscillator for low power mode */
   CLK0_TYPE,     /* Crystal or canned oscillator clock input */
   PLL_0,         /* PLL to initialize, in this case PLL0 */
   PLL0_PRDIV,    /* PLL predivider value */
   PLL0_VDIV,     /* PLL multiplier */
   MCGOUT);       /* Use the output from this PLL as the MCGOUT */
 /* Check the value returned from pll_init() to make sure there wasn't an error */
 if (mcg_clk_hz < 0x100)
  while(1);

Edit:

For information, in pll_init, return value is 0x11:

if (MCG_S & MCG_S_IREFST_MASK) return 0x11; // check bit is really clear and return with error if not set

I'm using the same as Tower K70 system (with external quartz of 12MHz).

I don't know if following configuration is Ok for that:

#define CLK0_FREQ_HZ  50000000
#define CLK0_TYPE           CANNED_OSC



#define CLK1_FREQ_HZ        12000000
#define CLK1_TYPE           CRYSTAL

/* Select Clock source */
/* USBHS Fractional Divider value for 120MHz input */
/* USBHS Clock = PLL0 x (USBHSFRAC+1) / (USBHSDIV+1)       */
#define USBHS_FRAC    0
#define USBHS_DIV     SIM_CLKDIV2_USBHSDIV(1)
#define USBHS_CLOCK   MCGPLL0


/* USB Fractional Divider value for 120MHz input */
/** USB Clock = PLL0 x (FRAC +1) / (DIV+1)       */
/** USB Clock = 120MHz x (1+1) / (4+1) = 48 MHz    */
#define USB_FRAC    SIM_CLKDIV2_USBFSFRAC_MASK
#define USB_DIV     SIM_CLKDIV2_USBFSDIV(4)




/* Select Clock source */
#define USB_CLOCK   MCGPLL0
//#define USB_CLOCK   MCGPLL1
//#define USB_CLOCK   MCGFLL
//#define USB_CLOCK   PLL1
//#define USB_CLOCK   CLKIN


/* The expected PLL output frequency is:
 * PLL out = (((CLKIN/PRDIV) x VDIV) / 2)
 * where the CLKIN can be either CLK0_FREQ_HZ or CLK1_FREQ_HZ.
 * 
 * For more info on PLL initialization refer to the mcg driver files
 */

#define PLL0_PRDIV      5

#define PLL0_VDIV       24

#define PLL1_PRDIV      5

#define PLL1_VDIV       30

#endif



extern uint32_t ___VECTOR_RAM[];

[arnogir]

Hello,

I modified the Loop constant from 2000 to 20000.:

for (i = 0 ; i < 20000 ; i++)
 {
 if (!(MCG_S & MCG_S_IREFST_MASK)) break; // jump out early if IREFST clears before loop finishes
 }
 if (MCG_S & MCG_S_IREFST_MASK) return 0x11; // check bit is really clear and return with error if not set

This work now, just the Frequency should not be ok, because Serial communication is not to the configured speed (Serial Com Ok when Debbuger P&E is plugged)

So I think I have a  problem of my constant value in Clock configuration, but I'm unable to know where, Clock system and PLL are very sofisticated.

[arnogir]

Any body can inform me about PLL configuration for my case?:smileycry:

[Jorge_Gonzalez]

Hello Arnaud Girard:

Sorry for the delay. I used the same bootloader project and ran into the same problem. Can you tell me your board schematic's version?

Depending on the version there is a jumper to enable the on-board 50 MHz oscillator (J18 or J19). See the manual http://cache.freescale.com/files/microcontrollers/doc/user_guide/TWRK70F120MUMfor details.

Please place the jumper and test again.

Regards!,
Jorge Gonzalez

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[arnogir]

Hello,

Like I said, I'm using a very similar tower K70 scheme, but not the Tower  K70.

I  attached the scheme of my board.

In fact there are two clock. One of 12MHz (Linked to the PTE24/PTE25) and other oscillator linked to "EXTAL_MAIN"

But how know which clock is selected?

[Jorge_Gonzalez]

Hello Arnaud,

Sorry, I did not read you have a custom board.

If you have the same clocking options as the TWR-K70F120M then the project should work without any changes. It's hard to say what is wrong since I don't have your board.

- In that bootloader project the 50 MHz oscillator is used as reference to get the system clock. Do you have a way to check the oscillator's output with a scope (U5-OUT), to see if there is clock?

- I also find strange that you have the signal RMII_CLKOUT shared between 50 MHz oscillator (U5) and 25 MHz crystal (Y3). Are both populated and active at the same time?

Regards!
Jorge Gonzalez

[arnogir]

Hello

This mornig I made the Test.

Then I restart the project, I have not make a new build, I had directly download the last build where problem occurs.

Then the problem occurs with and without the debugger.:smileyconfused:

50Mhz chrystal was Ok. (oscilloscope)

I stopped, and make a Clean to re build all. Then download. (Like I done last week!)

I downloaded and now, all work correctly, with and without debugger...

I made no change!:smileyconfused:

THe only difference with last week is codewarrior was stopped, computer was restarted...

Like I use SVN, there are two difference in the project.

The .elf is different (very minor difference), but this file is not easy readable...

and the .launch.

I attached here the two files. Some line are different.

Maybe you can read the difference and seen why with one all work and not with other?

:smileyhappy:

[arnogir]

Hello

Thank for your reply.

- I will check Clock Out and back here to inform you.

- Sorry, the 25MHz crystal is not mounted. So only the 50MHz goes to the ethernet Phy.

I think we must keep in our mind that all worked some month ago. I come back on this project now and all work with P&E debuger, but not working in standalone.

I don't think I change anything.. It is very strange.