Hi Mark,
Thanks for your information, I re-check the SHP register for the SysTick Interrupt Priority setting, and I found the value is set to 15, which is set by the API "SysTick_Config()".
So the SysTick priority value would be set to 15 if the SysTick_Config().
After call an extra NVIC_SetPriority(SysTick_IRQn, 0), then the SysTick can preempt the PIT ISR.
Besides, I have further questions:
1. I want to make sure that for SysTeck, the SHP3 register got 8 bits for setting up the interrupt priority.
Does it only provides the first MSB 4 bits (Bit7, 6, 5, 4) for setting up the priority, just like IPR register in NVIC?
2. Does the priority setting in the SHP1, SHP2 & SHP3 also follow the settings of the PRIGROUP setting in the AIRCR? So the priority value of SysTick would also be separated into GroupPriority and SubPriority, just like external interrupt setting in the NVIC IPR register?