Software stuck at function CLOCK_SYS_BootToPee() at startup

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Software stuck at function CLOCK_SYS_BootToPee() at startup

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ksk10
Contributor II

I am currently working on a custom hardware with Mk64fn1m0vll12 controller.

I have imported the gpio driver example project for frdm k64 board and changed the gpio pin to toggle led on one of the port pins.

When i start to debug the software , the code get stuck at CLOCK_HAL_GetFllSrc(MCG) . It continuously loops in the while loop where the above function is called.

Kindly suggest a workaround for this problem. Am I missing something for development on a custom hardware, or I can use the example project for frdmk64 as it is . 

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mjbcswitzerland
Specialist V

Hi

The FRDM-K64F has a 50MHz external oscillator as clock. If you use the same clock initialisation code for your board you will need to ensure the same 50MHz clock signal is available.

Regards

Mark

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ksk10
Contributor II

Hi,

Thank you for the prompt response. 

I am relatively new to kds , how can I set the clock frequency for my hardware.

Which ksdk APIs i need to refer. I am using a 25Mhz crystal .

I am also trying to use Processor expert, how do I set clock frequency in PE.

Regards,

Sanket 

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Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Sanket K,

If you are working with KSDK v1.3 and Processor Expert, the next document might be helpful to understand clock configurations:

https://community.nxp.com/docs/DOC-329554 

Regards!

Jorge Gonzalez

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mjbcswitzerland
Specialist V

Hi

No idea about the settings in the mentioned frameworks/case tools.

In teh uTasker project the K64F with 50MHz is set up like this:

        #define EXTERNAL_CLOCK       50000000                            // this must be 50MHz in order to use Ethernet in RMII mode
        #define _EXTERNAL_CLOCK      EXTERNAL_CLOCK
        #define CLOCK_DIV            20                                  // input must be divided to 2MHz..4MHz range (/1 to /24)
        #define CLOCK_MUL            48                                  // the PLL multiplication factor to achieve operating frequency of 120MHz (x24 to x55 possible)
        #define FLEX_CLOCK_DIVIDE    3                                   // 120/3 to give 40MHz
        #define FLASH_CLOCK_DIVIDE   5                                   // 120/5 to give 24MHz

To use 25MHz clock (which can't be used with Ethernet RMII) it needs:

        #define EXTERNAL_CLOCK       25000000                            // this would need to be 50MHz in order to use Ethernet in RMII mode !!!!!!!
        #define _EXTERNAL_CLOCK      EXTERNAL_CLOCK
        #define CLOCK_DIV            10                                  // input must be divided to 2MHz..4MHz range (/1 to /24)
        #define CLOCK_MUL            48                                  // the PLL multiplication factor to achieve operating frequency of 120MHz (x24 to x55 possible)
        #define FLEX_CLOCK_DIVIDE    3                                   // 120/3 to give 40MHz
        #define FLASH_CLOCK_DIVIDE   5                                   // 120/5 to give 24MHz

Regards

Mark

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