You can certainly implement a 'timer-banged' UART, ala' AN2637.
Reception can use virtually any GPIO -- set a falling-edge trigger to grab the leading edge of the 'start bit', then set a timer for 'somewhat less' than 1/2 bit-time (to compensate for interrupt-response on this, and the subsequent bit-interrupt), thence on that interrupt re-sample 'start' and if valid set 9 more 'full bit' timer-interrupts in succession to sample the input pin to build up the byte, and end by checking 'stop'. Variations in interrupt-response-time WILL affect the 'quality' of the 'center bit sampling'.
Sending is 'easier and better timed', but requires the use of a timer-output-pin. For each bit to send, you just set the 'software triggered' output mode, at the bit-width, and on each interrupt you set the NEXT 'state to set at timer expiration' per the next output-bit value. THIS interrupt-response time is 'relaxed' and only HAS to respond in less than a bit-time.