Using a K64 MCU - MK61FN1M0VMJ12
I want to transfer data into memory from an external peripheral AND transfer data from memory via high speed USB at the same time. Currently I am doing these operations sequentially.
I can't find information about the relative priority of the two BUS masters, is it documented?
I assume the two transfers will share the bus, only using the cycles needed.
Can anyone point me to some documentation on the topic?
Larry
Solved! Go to Solution.
Hi Larry,
The K64 reference manual chapter 3.3.6 shows the crossbar switch configuration.
The ARM core as Master0, DMA as Master2 and USB module as Master4 using crossbar to access slave device.
The K64 reference manual chapter18 shows how to set crossbar switch for master with different priority to access slave.
Wish it helps.
Have a great day,
Mike
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I finally have a working solution. Initially I used SRAM to hold buffers and HSUSB descriptors. This works well, but consumes a lot of SRAM.
I was able to get everything working in DDR by a combination of using the aliased DDR address space for USB descriptors and buffers and changing the crossbar priorities for the DDR (Slave 5) with HSUSB at the highest priority followed by eDMA then the ARM Core.
Hi Larry,
The K64 reference manual chapter 3.3.6 shows the crossbar switch configuration.
The ARM core as Master0, DMA as Master2 and USB module as Master4 using crossbar to access slave device.
The K64 reference manual chapter18 shows how to set crossbar switch for master with different priority to access slave.
Wish it helps.
Have a great day,
Mike
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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