Signal Halt received after setting PEE ext oscilator 50mhz

[alexpaul]

hello
I have problem with my eval board, i setted system oscilator to external reference clock 50mhz and PEE,pll mode with 100mhz core, 50bus, 25mhz flash, and after program, im always getting signal halt received, even if i set to stock clock settings, still getting this error while on secound board, with stock fei mode working fine. i have 50mhz oscilator on eval board, im using Codewarrior, tried to erase with commander, with success, but still error. Any ideas to unlock mcu? and why its bricked?

[Hui_Ma]

Hi Paul,

You could use P&E USB Universal Multilink tool to unsecure the Kinetis chip. When the secured chip doing debug the CodeWarrior software will pop up the mass erase window, you can select [Yes] to unsecure the chip. For the first used chip after manufactory will execute mass erase opertion, which will cause Flash configuration address 0x40C with value 0xFF, this value will be loaded to Flash Security Register and this value set the chip secured. You need to check if 50MHz oscilltor works and you could refer TWR-K60N512 board schematics about related clock circuit design.

http://cache.freescale.com/files/32bit/hardware_tools/schematics/TWR-K60N512-SCH_D.pdf

Wish it helps.

[alexpaul]

Im using Jlink Edu Segger, one time i saw unsecuring option, i chose to unsecure, i think it did nothing, becouse im still geting the same error, This board is K60 Mini Board from mcuzone.com, i checked that oscilator works, its okay. When i try using jflash arm 4,70 to erase, it looks:

Jlink foun 1jtag device Core id 0x4BA00477 Cortex M4

-reading cfi info

-could not find cfi compilant flash device
-detecting flash memory
-ERROR: Could not find any flash devices
-ERROR: Failed to connect

Still no idea to fix it. This board had demo firmware for present usb mass storage, and it worked.

[Hui_Ma]

Hi,

Could you available to check the demo firmware source code (usb mass storage)? It need to make sure the Flash configuratin filed 0x40C with [mass erase is enabled ] setting. Otherwise, it could not use external debugger tool to unsecure the chip. And if it have backdoor application to unsecure the board?

BTW: Segger provides Segger J-Link commander tool, which could use "unlock Kinetis" command to unsecure the Kinetis chip. While the presupposition is [mass erase is enabled] was set.

Thank you for the attention.

[alexpaul]

But it didn't helps, still the same error on PE_DEBUGHALT();

My settings after which is bricked

[Hui_Ma · Accepted solution]

Hi,

From Processor Expert configuration, there could not find any problem.

Please attention that Kinetis 100MHz product with two silicon version, more detailed info please check AN4445:

http://cache.freescale.com/files/32bit/doc/app_note/AN4445.pdf

And please select the correct the chip part number, the part number with "Z" character is Silicon 1.x product.

Could you enter into debug interface with [RAM] or [Flash] target?

And you code run into  PE_DEBUGHALT(); before or after enter into main() function.

Thank you for the attention.

[alexpaul]

You have right, i made mistake while using project for MK60DN512VLQ10,while the chip on this board is MK60DN512ZVLQ10 but using that in FEI mode did not make a problem.
I tried both programing Ram and Flash with no difference.
Im always getting Pe_debughalt always at 91line.
http://pastebin.com/0UkDFqXL
Any ideas to revive this board?

[Hui_Ma]

Hi Paul,

Could you upload your test project? And could you direct in which file line 91, the core will run into Pe_debughalt function.

Thank you.

[alexpaul]

Hi Hui Ma

I've already uploaded, take a look on the pastebin link
[C] /* ################################################################### ** T - Pastebin.com
Project is now just empty new bareboard project.

[Hui_Ma]

Hi Paul,

I can not open above link, could you post a picture and shows the line 91 info (better with file info).

Thanks.

[alexpaul]

[Hui_Ma]

Hi Paul,

I use CodeWarrior MCU V10.4 generate a PEE example project, I test this project works normal for TWR-K60N512 board (both Flash and RAM targets).

If you still meet above problem(enter into pe_debughalt function), I think that was caused by hardware issue.

For your evaluation board could works with FEI mode (chip reset MCG mode), the Kinetis chip should works normally.

I woule suggest you to contact with your evulation board vendor and if they could replace another board.

Wish it helps.

B.R.

Ma Hui

[GR8geek]

I am having same PE_DEBUGHALT() issue with TWR-K60D100M. I have tried my own and Ma Hui's attached project with same results. It seems that silicon on the Tower board is rev 2.x because it has 2N22D on second line of the physical device (ref: http://cache.freescale.com/files/32bit/doc/app_note/AN4445.pdf). The physical part is PK60DN512VMD10.

I am using CW10.4. and I am trying to get PDB to generate three pulse outs from comparators' outputs (How do I assign PDB Pulse-out signals to physical pins?)

Thanks,

-Irwin

[alexpaul]

I would like to thanks you all for help, finally i just resolder k60 chip and board just launched.
Now im trying to solve cau issue, i was waiting 2 weeks on service request with no respnse, Using CAU in K60 Chip [CW]
Regards Alex

[Kan_Li]

Hi Alex Paul,

Would you please give us some detailed info about the K60 device? such as part number and mask set on it. We will try to provide a PEE demo based on that and let you try on your board, then might have conclusion for the root cause.

Thanks for your patience!!

B.R

Kan

[alexpaul]

It looks that i have MK60DN512ZVLQ10 version on this board K60最小系统板，基于Freescale Kinetis K60DN512，QFP144封装，100MHz Cortex-M4 - Freescale开发板 Mcuzone 商城

[Kan_Li]

I see the PCB topview, looks no ref clock available, would you please tell us how you connect the 50MHz clock or crystal to the board? a picture should be better.

Thanks for your patience!!

B.R

Kan

[alexpaul]

Hi Kan
oscilator is on the bottom side of the board
And significant part of scheme

Kind Regards