Hi, Pang,
When the I2S is configured as master, the bit clock and frame clock sources are internal or external. This is the I2S clock source diagram for K70, I copy it from reference manual of K70.

Assume that the sampling clock is 48KHz, you use 32 bits data for left/right channel, the required bit clock frequecy BCLK is 64*48K=3.072MHz. No matter how you divide the clock source and where the clock source is, it is okay if the bit clock frequency is 3.072MHz.
There is not I2Sx_RCCR register for K70, probably you refer to wrong processor by mistake.
Assume that the core/system clock is 50MHz for your case, the Bit Clock Divider is 4, the MCLK must be 3.072M*4=12.288MHz, the MCLK frequency is 12.288MHz. 50MHz/12.288MHz=4.069, I suppose that you can set the FRACT=0, DIVIDE=3, it is okay. The actual bit clock will be 50MHz*1/(4*4)=3.125MHz.
as an alternative, assume that the core/system clock is 50MHz for your case, the Bit Clock Divider is 1, the MCLK must be 3.072MHz. The 50MHz/3.072MHz=16.276, I suppose that you can set the FRACT=99, DIVIDE=1626, it is okay, the actual MCLK will be 50MHz*(99+1)/(1626+1)=3.073MHz, it is okay.
This is the register setting, which I copy from RM of K70:

Hope it can help you
BR
Xiangjun Rong