Hello Peter,
I have checked your K65 benchmark application and I have also modified the write access by using eDMA (highest priority for the eDMA in the AXBS). But the performance is the same.
It seems that 57MB/s is the maximum for the SDRAM that is available on the K65 tower board.
Please, look at the block diagram of the Kinetis K-series (ARM Cortex M4), e.g. K70 block diagram:
The SDRAM memory chip is connected to the SDRAM (DRAM) controller of the MCU. The SDRAM controller is connected to a slave port of the Crossbar (internal bus), i.e. there is not direct access from CPU (or eDMA) to SDRAM, there must be always request to SDRAM controller that provides access to SDRAM memory without any cache. There is always delay to read/write data from/to SDRAM. In addition, there is always sequence of reading/writing data (ACTV, NOP, READ/WRITE, PALL) and refresh operations. Therefore the performance cannot be near to bus_clock x data_bus_width (e.g. 60 MHz x 4 bytes = 240MB/s). It also difficult to generate burst operation for the SDRAM controller by using internal bus. When I set the eDMA to use 32 bytes burst transfer size the performance is not higher.
In summary, the K65 design does not allow faster access to SDRAM because of the SDRAM memory chips connection to MCU by using SDRAM controller without caching of data.
Note:
I have found out an application note AN4745 - Optimizing Performance on Kinetis K-series MCUs (see http://www.freescale.com/files/microcontrollers/doc/app_note/AN4745.pdf). You can use it as a guide for configuration of your application for maximal performance.
When I use the eDMA to copy from internal RAM to internal RAM by using 32 bytes burst transfer size the performance is 321MB/s. There is not any delay caused by a controller and therefore the performance is higher.
Best Regards,
Marek Neuzil
Hi Peter,
I am sorry for confusion. The Code Cache can be enabled for the DRAM controller on the K65 derivative according to the reference manual. This cache can be used for access the SDRAM memory by the Program Code (I&D code) bus but the System Bus does not use any cache, see the following block diagram of K65 derivatives.
The K65 Reference Manual contains also following information:
30.4.1.1 Processor Code accesses
Processor Code accesses are routed to the SRAM_L if they are mapped to that space. All other PC accesses are routed to the Code Cache Memory Controller. This controller then processes the cacheable accesses as needed, while bypassing the non-cacheable, cache write-through, cache miss, and cache maintenance accesses to the CCM bus and the crossbar switch using the Master0 port.
30.4.1.2 Processor System accesses
Processor Space accesses are routed to the SRAM_U if they are mapped to that space. All other PS accesses are routed to the CCM bus and the crossbar switch using the Master1 port.
30.4.1.3 Backdoor port accesses
All LMEM backdoor port accesses are for the SRAM controller. These accesses go to the SRAM_L or the SRAM_U depending on their specific address.
The Optimizing Performance on Kinetis K-series MCUs application note contains the following information:
- ICODE - The ICODE bus is used for instruction accesses for any instructions stored between addresses 0x0000_0000-0x1FFF_FFFF.
- DCODE - The DCODE bus is used for data accesses for any instructions store between addresses 0x0000_0000-0x1FFF_FFFF.
- System - The system bus is used for all accesses to addresses between 0x2000_0000-0xDFFF_FFFF and 0xE010_0000-0xFFFF_FFFF
Therefore the only way how to use cache is the using of 0x08000000 - 0x08800000 memory area. But this memory area can be used in the write-through cache mode only (write-back mode is not available).
I will also send a question to an internal specialist about the usage of the cache and definition of cache regions. It is not clear from the description in the K65 reference manual.
Note:
Please, consider also the following information about write-back mode of the cache.
• A write-back write miss will do a "read-to-write" (allocate on write miss policy
for write-back mode spaces). A line read on the output bus of a 16 byte aligned
memory address containing the desired write address is performed. This miss
data is loaded into the cache and marked as valid and modified; and the write
data will then update the appropriate cache data locations.
It is mean, that writing into SDRAM memory performs reading of 16 bytes of memory into the cache and writing back into SDRAM memory. When you execute long sequence of writing into SDRAM it leads to reading and writing of the whole memory block from/to SDRAM.
Best Regards,
Marek Neuzil
Hi Peter,
You are right, the only CODE from SDRAM can be cached (Region 1). The K65 core CPU can use the following regions only (R5-R15 regions are not available because the System Cache is not available on K65).
(I have received a confirmation of this fact from a Freescale specialist)
Note:
The SDRAM controller contains 16-bytes buffer. It should be able to buffer at least 16-bytes of data (line transfer size).
Best Regards,
Marek Neuzil
Hi Peter,
The K70 derivatives contains both caches (for code bus and system bus of the Core), see the following block diagram (K70 subfamily reference manual):
You can use R7 and R8 cache regions to configure cache access to the SDRAM (from the Core):
Note:
R7 region cache mode is is write-back by default (after reset state)
R8 region cache mode is is write-through by default (after reset state)
See details in the Chapter 28 Local Memory Controller in the reference manual of the K70 subfamily.
Best Regards,
Marek Neuzil
