Relocate verctor table

[danielchai]

Hi all,

I read the manual for freescale TWR-K60N512.

It said " The Cortex-M4 assumes the RAM starts at 0x20000000 and expects the vector table to be stored in that address if the VTOR TBLBASE[29] bit is set. Because the Kinetis MCU family RAM starts at 0x1fff0000, this bit must be cleared" but it slaso said " Use the bit TBLBASE[29] to indicate the table is either on RAM with 1 or

flash with 0 ", so if in Kinetis MCU familly, I want to relocate the vector table, what should I do? Should I clear  TBLBASE[29] bit or set it?

Thanks.

-Daniel

[ronkim]

As the other posts have indicated, SCB_VTOR should contain the base address of the flash vector table or the base address of the RAM vector table. So, if you are re-locating the vector table to RAM (somewhere between 0x1FFF_0000 and 0x1FFF_FFFF), then software should clear SCB_VTOR[29] to 0.

[dieterteuchert]

The table base is just a pointer variable and should contain either the base address of the FLASH vector table or the base address of the RAM vector table. At boot time the pointer points to flash. Once a RAM table has been setup (at least the 16 core vectors), the pointer can be the address of that RAM table.

Main risk of error is getting the correct alignment of the RAM table. Apparently the core does not use an adder for the calculation of a vector location, but a bit field combiner. Therefore the whole table must be aligned to a 256 byte, 512 byte or 1024 byte boundary, rounding up the size of the table in bytes (number of vectors * 4). When the table alignment is bad, the NVIC will pick lower vectors for higher interrupts, a confusion that will ruin everything else.

Except of alignment you can put the vector table where you like.

[ndavies · Accepted solution]

Just copy the upper 25 bits of your vector tables starting address into the register. If your RAM vector table is between  0x1FFF0000 and 0x1FFFFFFF bit 29 will be clear, if your vector tables start address is above 0x20000000 bit 29 will be set. 2^29 = 0x20000000. The ARM docs expect RAM to start at 0x20000000, Freescale placed the RAM at 0x1FFF0000. So the bit 29 note from ARM doesn't translate correctly to Freescales implementation.