Regarding errata e10180

[aporvasrivastava]

Hi Team,

While analyzing errata e10180, description says that Clock switch may hang if SCG_RCCR is written to the switch system clock source with a different divide ratio while an external reset is asserted.

I have doubt that controller is getting up and external reset is de-asserted then how software can updated SCG_RCCR register when external reset is asserted. 

Please let me know if this understanding is correct ?

[bobpaddock]

Where do I find this Errata?

Did not find it via using search on NXP site.

[jingpan]

Hi,

Please get from here

https://www.nxp.com/docs/en/errata/Kinetis_E_0N79P.pdf

Regards

[bobpaddock]

Thank you.

[jingpan]

Hi @aporvasrivastava ,

The risk of clock hanging during switch is due to the internal timing, the scenario is: The silicon is booting up on FIRC and then the RCCR register is written by user's code to switch the system clock to SIRC. But as soon as the RCCR register is written as SIRC clock, the external reset is asserted, due to which the SCS bus moved to RESET value which is FIRC, but the SCS_NEXT stayed at 'h2 (SIRC) as ipg_clk is cut on reset. due to reset while boot up again the clock process is hanging as the SCS and SCS_NEXT is not matching due to scs_next not resetting.

Regards,

Jing