ROM bootloader WriteMemory fails

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

ROM bootloader WriteMemory fails

ソリューションへジャンプ
1,215件の閲覧回数
richardmoran
Contributor II

Hi everyone.

I'm trying to program some KL27s using the ROMN bootloader via SPI in a custom circuit and I am unable to write to memory using the WriteMemory command.

I use the FlashEraseUnsecure command then do the WriteMemory command which gets nacked at the first data packet.

Below a a capture of the packets sent over the SPI bus when attempting to set 100 bytes at address 0 to 0xA2

erase cmd                  5A A4 4 0 F6 61 0D                             

ack                             5A A1                                  

Generic response      5A A4 0C 0 54 81 A0 0 0 2 0 0 0 0 0D 0 0 0                  

ack                             5A A1                                  

write cmd                   5A A4 0C 0 6D 3A 4 1 0 2 0 0 0 0 64 0 0 0 0 0                

ack                             5A A1                                  

Generic response      5A A4 0C 0 23 72 A0 0 0 2 0 0 0 0 4 0 0 0                  

ack                           5A A1                                  

data  packet             5A A5 20 0 B4 B0 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2                                 A2 A2 A2 A2 A2 A2 A2 A2 A2

nack                         5A A2     

Does anyone have any ideas what I'm doing wrong?

Cheers,

Rich

ラベル(1)
0 件の賞賛
返信
1 解決策
1,038件の閲覧回数
richardmoran
Contributor II

Problem solved!.

I had a subtle bug in the calculation of the data packet crc.

Thanks for the help.

元の投稿で解決策を見る

0 件の賞賛
返信
3 返答(返信)
1,038件の閲覧回数
bobpaddock
Senior Contributor III

What activity is going on, on other ports?  I've had problems with the 27 bootloader loading from USB if there is serial activity on a UART.

0 件の賞賛
返信
1,038件の閲覧回数
richardmoran
Contributor II

There's no other activity going on.  LPUART0 and 1 are not connected to anything at the moment and I'm not using I2C. 

Apart from the SPI, it's all digital I/O which aren't changing states and 1 channel of ADC, which should be disabled in bootloader mode anyway.

0 件の賞賛
返信
1,039件の閲覧回数
richardmoran
Contributor II

Problem solved!.

I had a subtle bug in the calculation of the data packet crc.

Thanks for the help.

0 件の賞賛
返信