PLL for KV58

[#1]

The documentation points out that the Figure 32-1. Multipurpose Clock Generator (MCG) block diagram in KV5xP144M240RM.pdf is incorrect, the  /2 divider is NOT included in the feedback loop. It gives the formula to compute the VCO and MCGPLLCLK clock frequency and corresponding code.

[Masmiseim]

Hello,

is this also true for other Kinetis derivates with a /2 in the feedback-loop like the K66 or K80?

Thanks and regards

[xiangjun_rong]

Hi, Markus,

Firstly, this is the documentation error instead of PLL problem itself.

The documentation error only happens in KV5x, the documentation in K65 and K66 is correct.

Hope it can help you

BR

Xiangjun Rong