I indicated the measurements of the hull conclusions which gave precisely incorrect measurements. These are the channels of HSADC0 ANB11, ANB10, ANA12, ANA11, ANA10, ANA7 they all did not correctly measure
Correctly measured channels of ANA3 ANA2 ANA4 which do not pass through the multiplexer of the second level of channels 6 to 7
Good afternoon Xiangjun Rong
I set your settings but changed ADC0A_HC3 to signal type not differential. I also closed all contacts on 2.3.19.28 on AGND or VREH received such data after conversion (see photo). I use my VREFL processor contact board is shorted to AGND and the VREFH contact is closed to the 3.0V reference voltage source of the qfp100 processor case. How do you think it can be wrong to calibrate if the input voltage is applied immediately? What tests do you need?
Here is my listing
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/*
Good day
I use MKV58F1M0vl24 in the case of QFP100
I need to use the second HSADC0 multiplexer and channels from 6-12 and the corps leads 28,21,20,19,18,15,14 which are not ports of input-output. As is known, the inputs of HSADC0 from 6-channel and further multiplexed by the HSADCx_MUX67_SEL register. And I'm using a non-differential input mode. External reference voltage source 3V. Power of VDDA 3.3V. A quartz oscillator 25MHz for clocking is external used. The core frequency is 200 MHz.
The problem is the following when I try to convert from inputs number 6 and more values ??are obtained not true and when at input 0V (input is closed to ground) the value does not drop to 0 it can be about 0x200. Also, if a 2000 ohm resistor is connected to the input by one contact and the second one is connected to the ground at the input, there is a voltage of about 2.5V. Conversion from inputs 0-5 is excellent and correct. I took an example from KDK2.0 on the work of HSADC0 changed the channel numbers to the ones I needed to set up the settings for my kernel clock and HSADC0 mode. Maybe you can tell me something?
I attached my project to the IAR ARM you can see it*/
#include "fsl_debug_console.h"
#include "board.h"
#include "fsl_hsadc.h"
#include "pin_mux.h"
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* HSADC base address. */
#define DEMO_HSADC_INSTANCE HSADC0
/* The converter A's channels to sample. */
//Channel Index: pin 19, HSADC0A_CH3/HSADC1A_CH3
#define DEMO_HSADC_CONVA_CHN_NUM1 3U /* Configuration combination 1, ADCA_CH2 and ADCA_CH3 */
#define DEMO_HSADC_CONVA_CHN67_MUX_NUM1 0U
#define DEMO_HSADC_CONVA_CHN_NUM1_ENABLE_DIFF false
//Channel Index: pin 28, HSADC0A_CH12/CMP0_IN4/CMP2_IN3
#define DEMO_HSADC_CONVA_CHN_NUM2 6U /* Configuration combination 2, ADCA_CH6D */
#define DEMO_HSADC_CONVA_CHN67_MUX_NUM2 3U
#define DEMO_HSADC_CONVA_CHN_NUM2_ENABLE_DIFF false
/* The converter B's channels to sample. */
//Channel Index:pin3, PTE2,HSADC0B_CH10/HSADC1B_CH0
#define DEMO_HSADC_CONVB_CHN_NUM1 6U /* Configuration combination 2, ADCB_CH6C(PTE2) */
#define DEMO_HSADC_CONVB_CHN67_MUX_NUM1 2U
#define DEMO_HSADC_CONVB_CHN_NUM1_ENABLE_DIFF false
//Channel Index:pin2, PTE1, HSADC0B_CH17/HSADC1A_CH1
#define DEMO_HSADC_CONVB_CHN_NUM2 7U /* Configuration combination 2, ADCB_CH7F(PTE1) */
#define DEMO_HSADC_CONVB_CHN67_MUX_NUM2 5U
#define DEMO_HSADC_CONVB_CHN_NUM2_ENABLE_DIFF false
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/*!
* @brief Main function
*/
int main(void)
{
hsadc_config_t hsadcConfigStruct;
hsadc_converter_config_t hsadcConverterConfigStruct;
hsadc_sample_config_t hsadcSampleConfigStruct;
uint16_t sampleMask;
BOARD_InitPins();
BOARD_BootClockHSRUN();
BOARD_InitDebugConsole();
PRINTF("HSADC dual parallel conversion example.\r\n");
/* Initialize the HSADC common digital control.
* "kHSADC_DualConverterWorkAsTriggeredParallel" and simultaneous mode is used in this case. The two conversion
* sequence would be executed by each converter at the same time. Both converter shares the converter A's control
* logic such as start, stop, DMA enable, sync input etc.
*/
HSADC_GetDefaultConfig(&hsadcConfigStruct);
HSADC_Init(DEMO_HSADC_INSTANCE, &hsadcConfigStruct);
/* Configure each converter. */
HSADC_GetDefaultConverterConfig(&hsadcConverterConfigStruct);
/* Enable the calibration in power up period. */
hsadcConverterConfigStruct.clockDivisor= 9;
hsadcConverterConfigStruct.samplingTimeCount =250;
hsadcConverterConfigStruct.powerUpCalibrationModeMask =
(kHSADC_CalibrationModeSingleEnded | kHSADC_CalibrationModeDifferential);
HSADC_SetConverterConfig(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, &hsadcConverterConfigStruct);
/* Enable the power for each converter. */
HSADC_EnableConverterPower(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, true);
while (
(kHSADC_ConverterAPowerDownFlag | kHSADC_ConverterBPowerDownFlag) ==
((kHSADC_ConverterAPowerDownFlag | kHSADC_ConverterBPowerDownFlag) & HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE)))
{
}
/* Wait the calibration process complete. None End of Scan flag will be set after power up calibration process. */
while ((kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag) !=
((kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag) &
HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE)))
{
}
HSADC_ClearStatusFlags(DEMO_HSADC_INSTANCE,
(kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag));
/* Make each converter exit stop mode. */
HSADC_EnableConverter(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, true);
/* Configure the samples. */
HSADC_GetDefaultSampleConfig(&hsadcSampleConfigStruct);
/* For converter A. */
hsadcSampleConfigStruct.channelNumber = DEMO_HSADC_CONVA_CHN_NUM1; //Rong Wrote:ADC0_ANA3
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVA_CHN67_MUX_NUM1;
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVA_CHN_NUM1_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 0U, &hsadcSampleConfigStruct);
hsadcSampleConfigStruct.channelNumber = DEMO_HSADC_CONVA_CHN_NUM2; //Rong Wrote: ADC0_CH6
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVA_CHN67_MUX_NUM2; //ADC0_CH12, pin 28
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVA_CHN_NUM2_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 1U, &hsadcSampleConfigStruct);
/* For converter B.
* In HSADC_SetSampleConfig(), the channel number 0~7 represents input 0~7 of converter A and channel number 8~15
* represents input 0~7 of converter B.
*/
hsadcSampleConfigStruct.channelNumber = (DEMO_HSADC_CONVB_CHN_NUM1 + 8U);
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVB_CHN67_MUX_NUM1;
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVB_CHN_NUM1_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 8U, &hsadcSampleConfigStruct);
hsadcSampleConfigStruct.channelNumber = (DEMO_HSADC_CONVB_CHN_NUM2 + 8U);
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVB_CHN67_MUX_NUM2;
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVB_CHN_NUM2_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 9U, &hsadcSampleConfigStruct);
/* Enable the sample slot.
* The conversion sequence for converter A includes sample slot 0 and 1, while the sequence for converter B
* includes sample slot 8 and 9. Sample slot 0~7 can reference only to converter A and sample slot 8~15 can
* reference only to converter B in parallel mode.
*/
sampleMask = HSADC_SAMPLE_MASK(0U) /* For converter A. */
| HSADC_SAMPLE_MASK(1U) /* For converter A. */
| HSADC_SAMPLE_MASK(8U) /* For converter B. */
| HSADC_SAMPLE_MASK(9U); /* For converter B. */
HSADC_EnableSample(DEMO_HSADC_INSTANCE, sampleMask, true);
HSADC_EnableSample(DEMO_HSADC_INSTANCE, (uint16_t)(~sampleMask), false); /* Disable other sample slots. */
PRINTF("Press any key to trigger the conversion ...\r\n");
PRINTF("\r\nSample 0\tSample 1\tSample 8\tSample 9\r\n");
while (true)
{
PRINTF("\r\n");
/* Trigger the converter.
* Trigger converter A would execute both converter's conversion when in
* "kHSADC_DualConverterWorkAsTriggeredParallel" and simultaneous work mode.
*/
/// GETCHAR();
HSADC_DoSoftwareTriggerConverter(DEMO_HSADC_INSTANCE, kHSADC_ConverterA);
/* Wait the conversion to be done. */
while (kHSADC_ConverterAEndOfScanFlag !=
(kHSADC_ConverterAEndOfScanFlag & HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE)))
{
}
/* Read the result value. */
if (sampleMask == (sampleMask & HSADC_GetSampleReadyStatusFlags(DEMO_HSADC_INSTANCE)))
{
PRINTF("%d\t\t", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 0U));
PRINTF("%d\t\t", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 1U));
PRINTF("%d\t\t", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 8U));
PRINTF("%d", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 9U));
}
HSADC_ClearStatusFlags(DEMO_HSADC_INSTANCE, kHSADC_ConverterAEndOfScanFlag);
}
}
