Multiprocessor Kinetis

[dieterteuchert]

While i have made good progress on implementing and optimizing DSP procedures for Cortex M4, i was wondering if there was ready to use support for multiprocessor solutions, for example a debugger that works with an oldfashioned JTAG chain including two or four MK10 processors and which could be used to initialize flash on such a board. As far as i remember, the main problem with FPGA embedded multiprocessor solutions was debugging them.

[Hui_Ma · Accepted solution]

Hi,

Kinetis product supports JTAG chain. Customer can select to use Segger J-Link tool or UNLINK2 debugger tool to control the chain.

More detailed info, please check below link:

http://www.segger.com/admin/uploads/productDocs/UM08001_JLinkARM.pdf

& http://www.keil.com/support/man/docs/ulink2/ulink2_su_chaining.htm

There also need to do some modification with debug interface, please check attached file as a reference.

Wish it helps.

[dieterteuchert]

Thank you for your support. During my DSP benchmark tests i also used an STM32F407 for comparison, and i found that the STM32 was loosing cycles when executing from RAM. It has some 1-cycle RAM, but cannot execute from that range of memory. So a 2 processor  K10 77 MHz system is cheaper and more powerful than a 180 MHz STM32, i mean as integer DSP. And the new STM32 parts with TDM I2S are not available yet.

Another question: Do the 100, 120 and 150 MHz Kinetis variants all execute from 1-cycle RAM?

[Hui_Ma]

Yes, Kinetis 100MHz, 120/150MHz products all with 1-cycle access SRAM.

Thank you for the attention.