Minimal K20 breadboard prototype

[rogerfl]

My goal here is to just make a "hello world" prototype to test using internal voltage regulator, internal clock, JTAG interface, and a uart console.  I have not added any connections to the UART yet.  See pic below.  All the wires going off the left edge are not connected to anything - they are meant to be connected to the JTAG debugger (PEM Multilink Universal with standard ARM connector) but not yet.

Ignoring the disconnected JTAG wires, connections are

VREGIN -> +5V from 7805 voltage regulator with caps 100u on input, 1u on output

VDD (both) -> VOUT33 with .1u decoupling caps

VSS (both) -> ground

RESETb -> 10K pullup with a 1u cap (which I don't think I need) to VOUT33

This MCU is MK20DX128VL5.

Happy to report that VOUT33 looks stable. I had to add some of the caps above to cleanup the 5V to get that working.

My problem is that RESET never goes high.

What have I missed? Any ideas on why the RESET pin always measure ~0V, why MCU is not coming out of reset and releasing the RESET pin?

10

[Robin_Shen]

1. Turn off the board system.

2. Assert the reset pin and hold it asserted for the remainder of the process.

3. Power on the board

4. Start a debug session and as soon it is starting release the reset button. This will force the debug session to enter.

For further reset connection recommendations refer to the Kinetis Quick Reference User guide: http://cache.freescale.com/files/32bit/doc/quick_ref_guide/KQRUG.pdf?fpsp=1 Section "2.3.4.1 RESET_b and NMI_b"

Hope this helps.

[rogerfl · Accepted solution]

Just a followup... apparently the NMI_b pin needs to be pulled high during start because when I added that the MCU was able to be programmed by the debugger just fine.

[rogerfl]

I do not have anything connected to NMI_b so I'm hoping that's the problem. Unfortunately that project is in a different state than I until Monday. Will let you know next week.

From studying the ref manual more, I see that NMI_b pin is also EzPort Chip Select, which if asserted (low), on reset will cause chip to enter EzPort enabled mode.  So, I plan to add connection from NMI_b to 3.3V with a 10K resistor and a .1 uF cap.

Would love to hear opinions on that theory.

Regarding the synchronization of steps for reset, I hope that is not necessary. And would love an explanation of why it would be necessary.

Thanks Robin.

Roger

[hectorsanchez]

1.- Make sure every ground is connected, can't see if the pin3 (Ground) of the 7805 is connected to the other grounds.

2.- Change the 1u cap on the RESETb , it's probably damaged

Keep me informed , i'm checking the schematic for problems

[rogerfl]

Thank you for taking a look.

1. It is pin 2 of the 7805 that is ground. Maybe there are more than one "7805." This is ON Semiconductor MC7805CTG. The inside rails of the breadboard are connected to pin 2 of the 7805.

2. Changed the reset_b cap; no change. Tried without the cap; no change.

I was wondering if the analog power is required to be connected for the MCU to start (VSSA, VDDA). Are they required?

[hectorsanchez]

Those are not necessary ,

I found this in the Reference guide provided by Robin:

"Critical input pins, like RESET_b and NMI_b should have 100 nF capacitors close to the MCU for transient protection. Each pin has a weak internal pullup, but an external 4.7 kΩ to 10 kΩ pullup is recommended."