Mass erase not completing on KL26

[kevincuzner]

I've been working on getting an SWD dongle working. So far I've managed to program the flash on a KE04, but moving on to some KL26's I ran into some trouble. I've been following the instructions here under SWD mass erase. Here is the procedure that I've been doing:

• 5V is applied to the internal 3.3V regulator and the 3.3V is ran into the VDDs
• The reset line is tied to ground
• I read the IDCODE register from the SWD and it is correct.
• I read the MDM-AP status reguster and it reads 0x36. I've interpreted this to mean mass erase is enabled, the device is secured, and the flash is ready.
• I write the MDM-AP control register with 0x1 which I believe should start the mass erase procedure
• I read MDP-AP control repeatedly waiting for the 0th bit to clear. There is about 0.1s between reads of this register

The issue I've been having is that the last step goes on for a long time (indefinitely it seems, but I've only tested it for a couple minutes). This procedure worked fine to un-secure on a KE04 (except I didn't have to tie reset low). I'm hoping that somebody might know some detail about the differences between the mass erase procedure via SWD between KE04 and KL26 devices and that perhaps I'm doing something wrong.

Is it also possible the device has been damaged while soldering it to my board? The chip has never been programmed before, so I would have expected it to come in a non-secure state.

[Jorge_Gonzalez]

Hello Kevin Cuzner:

Sorry for the delay with no answers.

Are you using any programming tool in particular or just bit banging the SWD?

I don't think the reset line must be permanently tied to ground. Did you read any document indicating such connection?

Regards!
Jorge Gonzalez

[kevincuzner]

I'm just bit banging SWD. I don't believe there are any errors with my implementation as it seems to communicate fine to the device. However, my sequence of events could be just wrong. Also, there is significant SWD clock jitter as it is raspberry pi doing the bitbanging. Is it possible that the jitter could be causing problems?

The document I referenced about flash programming for L devices said that the reset line needed to be held low during the whole erase process (last paragraph in Section 4.2.2.1).

I've tried this on two chips with the same result. Two factory fresh chips that read as secure tells me that something is wrong. Am I not interpreting the register values correctly?