It mean that if you want to use DIO1 and DIO0 in enhanced mode, you should route these signals to PTC4 & PTC3 pins, instead use them on default pins (PTE3 & PTE2).
The reason for this is explained on 8.1 LGA Package Maximum Ratings in the datasheet MKW01Z128:
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
Have a nice day :P,
Perla
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------