I2C SCL Start & Hold Times

[LSmith-NK]

In the K12 Sub Family reference manual, document # K12P80M50SF4RM, there is Table 42-41, which is the I2C Divider and Hold Values table. Is there a diagram anywhere that shows what the SDA Hold Value and the SCL Hold Start/Stop Values are?

Also, it says those values are in 'Clocks', so does that mean that if I am running at 8Mhz, then the SCL Hold Value for the first entry in that table would be 7/8000000, or 875 nanoseconds? It is just unclear to me, so any info will be much appreciated. Thank you

[LSmith-NK]

Thank you Ma! This does solve the question.

[Hui_Ma · Accepted solution]

Please related the SDA hold time, the SCL start hold time, and the SCL stop hold time interpretation at I2C Frequency Divider register (I2Cx_F) [ICF] bit description.

It located at page983 of K12P80M50SF4RM.

It also provides an example.

Wish it helps.

Best regards,
Ma Hui

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------