MKE02Z FRDM_KE02Z40M SPI Communication TxBuffer not copied

[archy404]

Hey,
I am Trying to Implement an SPI communication between the Freescale FRDM_KE02Z40M and the ESP32S3.

The ESP32S3 sends 32byte of data. The FRDM_KE02Z40M should send 32 byte back.

However, while the data send by the ESP is recieved correctly, only the first byte of the data the FRDM_KE02Z40M should send is actually transmitted. After that, the ESP32 only recieves his own transmission repeated back to him.

 (Data recieved by the MKE02Z)

The relevant code of the ISR looks like this:

void spi_slave_irq(spi_handle_t *handle){
uint8_t flags = spi_getStatusRegister();
//Check wether the Transmit Buffer empty flag is set and if so, write the next 8 bit to SPI0_D
if(((flags & 0xFFU) & SPI_S_SPTEF_MASK) != 0)
{
spi_write_shiftregister(*(handle->txData));
handle->txData++;
handle->txindex++;
}
//Check wether the Recieve Buffer full flag is set and if so, read the next 8 bit from SPI0_D
if(((flags & 0xFFU) & SPI_S_SPRF_MASK) != 0)
{
*(handle->rxData) = spi_read_shiftregister();
handle->rxData++;
handle->rxindex++;
}
...

The RxBuffer Full Flag is reliantly set during transmission and the shiftregister copied to the rxbuffer every 8 bit.

However, the TxEmpty Statusflag is never set during a Transmission but only BEFORE and AFTER it. Which leads me to the assumption, that the TxBuffer is not copied to the shift register of the SPI Module during the Transmission.

This makes sense, as if the TxBuffer is not copied to the shift register the data recieved from the ESP32 would stay on the shift register and be repeated back to it the next 8 shifts.

Is this Problem known? Is there a configuration or a option i missed?
The error also exists within the example projects provided by nxp.

[archy404]

Hi Eduardo,

Thanks for your reply. I attached two captures. The Capture "Logic_Analyzer.png" shows the behaviour with a continous SS signal. The file "Workaround.png" Shows how the data can be transmitted reliantly. If i only transmite 1 byte at a time, everything works. However this is not a viable Solution for a Product, since this slows down transmission 50 fold.

The transmission function of the ESP is based on their framework:

void spi_communicate(uint8_t* txData, uint8_t* rxData){

for (int i=0;i<FRAMESIZE ; i++) //This is the workaround. Normally. length would be FRAMESIZE * 8 and .txbuffer would be txData instead of txData++
{
spi_transaction_t transmission = {
.flags = 0U,
.length = 1* 8,
.rxlength = 0,
.user = NULL,
.tx_buffer = txData++,
.rx_buffer = rxData++
};
spi_device_transmit(spi_handle, &transmission);
}
}

Documentation of the ESP-IDF can be found here: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/spi_master.htm...

SPI Initialization ESP:

void spi_initialize(void){

spi_device_interface_config_t slave_device_config = {
.command_bits = 0,
.address_bits = 0,
.dummy_bits = 0,
.mode = 0,
.duty_cycle_pos = 0, //0 equals 50% duty cycle
.cs_ena_pretrans = 0,
.cs_ena_posttrans = 0,
.clock_speed_hz = 10*1000*1000,
.input_delay_ns = 75, //may be further adjusted. taken from ESP32 to ESP32 values
.queue_size = 1,
.spics_io_num = SPI_CS_1,
.flags = 0U,
.pre_cb = NULL,
.post_cb = NULL
};

spi_bus_config_t bus_config = {
.mosi_io_num = SPI_MOSI_PIN,
.miso_io_num = SPI_MISO_PIN,
.sclk_io_num = SPI_SCLK_PIN,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
.data4_io_num = -1,
.data5_io_num = -1,
.data6_io_num = -1,
.data7_io_num = -1,
.max_transfer_sz = 0,
.flags = 0U,
.intr_flags = ESP_INTR_FLAG_LEVEL1
};

MKE02 Setup:


void spi_initialize(){
CLOCK_EnableClock(spiClock);
//Disable SPI0 during configuration
spi0_registers->C1 &= (uint8_t)(~SPI_C1_SPE_MASK);
//configure C1 and C2 register. Master/Slave, CPOL, CPHA, LSBFE. C2 is all zero for slave.
spi0_registers->C1 = SPI_C1_MSTR(0U) | SPI_C1_CPOL(SPI_CPOL) | SPI_C1_CPHA(SPI_CPHA) | SPI_C1_LSBFE(SPI_LSBFE);
spi0_registers->C2 = SPI_C2_SPMIE(0U) | SPI_C2_SPISWAI(0U) | SPI_C2_BIDIROE(0U) | SPI_C2_SPC0(0U);
//configure RX Full and TX Empty Interrupts
spi0_registers->C1 |= SPI_C1_SPIE_MASK | SPI_C1_SPTIE_MASK;
//reenable SPI0
spi0_registers->C1 |= SPI_C1_SPE_MASK;
}

[EduardoZamora]

I appreciate the details.

Could you please help me with the version of the SDK you are using?

Also, would it be possible to test the communication with a clock speed less than 5MHz? The SPI interface of FRDM-KE02Z40M configured as a slave runs at a maximum of the bus clock divided by 4, equivalent to 5MHz and I understand that your master setup indicates a clock speed running at 10MHz.

Regards,
Eduardo.

[archy404]

Hello Eduardo,

Could you please help me with the version of the SDK you are using?

I am Using Keil IDE v5.
In that IDE I am Using the provided Board SoftwarePacks.
Namely:

NXP.MKE02Z4_DFP.14.0.0 (version 14.0.0 01_05_22) // Board Support Pack for FRDMKE02Z40M
This is according to description based on the MCUXpresso SDK 2.11.0

The Used CodeBase is that of the Example Programm, the Spi Driver fsl_spi was replaced with the one i wrote myself based on the information provided in the Reference Manual. (But i only did this after the fsl_spi as well as the cmsis driver caused the same described error)

Also, would it be possible to test the communication with a clock speed less than 5MHz? The SPI interface of FRDM-KE02Z40M configured as a slave runs at a maximum of the bus clock divided by 4, equivalent to 5MHz and I understand that your master setup indicates a clock speed running at 10MHz.

Okay, i was not aware, since several references claim the board to operate at 40MHz, like

Kinetis KE02-40 MHz, robust Microcontrollers (MCUs) based on ARM Cortex-M0+ Core

However, I already tested the error at several different speeds down to 100 kHz, the Problem remained the same with all tested speeds. I only ramped up the speed after, to fasten up the transfer at least a little bit, with the workaround of sending one byte at a time.

[EduardoZamora · Accepted solution]

Thank you for your reply.

As I understand, the slave interface configured in your master indicates that it is using mode 0, which means CPOL = 0 and CPHA = 0, according to the ESP-IDF Documentation.
As indicated in the KE02 reference manual: SPI clock formats, when C1[CPHA] = 0, the slave's SS input must go to its inactive HIGH level between transfers. Taking a look at the capture "Logic_Analyzer.png", SS signal remains LOW between successive transmissions. Would it be possible to test the transmission configuring the master so that the SS signal goes to HIGH level between transfers? I would like to ask you to help us by using the original driver.

Besides that, I apologize for the misunderstanding. The information you have is correct, the core clock operates at 40MHz, but the bus clock operates at the core clock divided by 2 and the SPI interface runs up to the bus clock divided by 4.

[archy404]

Thank you for your help. Please forgive me for using up your time.

[EduardoZamora]

Hi, Achim.

Could you please attach a capture of MISO, MOSI, CLK and SS signals? Either with a logic analyzer or oscilloscope. Also, it would be helpful if you share with us both your master and slave setup.

Just to be sure, does your master setup require a continuous SS signal?

Regards,

Eduardo